Currently, the development of electronic devices is carried out using a microcontrollers (MC), containing one or more analog-to-digital converters (ADC). Sometimes, ADC for MC do not meet the requirements of accuracy and noise. In this regard, the scientific and production division "Dozor" has developed a new type of ADC with the phase locked loop (PLL) . The closest prototype of ADC with PLL is stable frequency synthesizer. Such synthesizers are used as reference oscillators in frequency converters, electronic musical instruments and many other devices. Fig.1 shows a functional diagram of the frequency synthesizer. The output signal of the synthesizer is an alternating voltage with a frequency FГУН = N∙F1. Accuracy and stability of frequency have to meet high requirements. ADC uses intermediate conversion of the analog signal (voltage) into the pulse by means of PLL . A detailed description of the working principle of PLL is given in [2, 3]. Functional diagram of the ADC with PLL is presented in Fig.2. ADC with PLL contains elements of the synthesizer and additional elements (in the diagram circled by dashed lines). The main ones are the following functional blocks:
• reference voltage source is a required element of ADC. Amplitude of the output pulses of the phase detector is equal to the reference voltage Up, and the pulse duration TX is equal to the phase shift between the signals F1 and F0; • low-frequency filter (LFF) designed as a proportionally-integrating (PI) filter with additional input for external signal (Ux), which is converted into pulse width, and then into a binary code; • PI filter provides the astaticism of the PLL system, that is, the steady-state average values of the output signal of the phase detector UФД and of the input signal Ux are always equal. Thanks to the integrator and a negative feedback, the input voltage of VCO is maintained so that the frequency of the signals F1 and F0 are equal. Phase shift Tx between signals F1 and F0 is equal to Tx = T1∙Ux/Up, where T1 is the period of frequency F1, Ux is input voltage, Up is reference voltage of the ADC; • RAM for storing the current value of the binary code. Code is written in the time of the leading edge of the pulse signal F0; • pulse phase detector (PD) based on logic elements and having a linear output phase characteristic to ensure high precision conversion. In ADC with PLL the signals of the two oscillators F1 and F0 are internal, their form of voltage needs to be rectangular, to ensure the operation of pulse PD. Since PD measures the time interval between leading edges of the pulses F1 and F0, the off-duty ratio of these pulses does not affect the measurement accuracy of the phase shift. In 2012 the scientific and production division "Dozor" has developed a 15-channel information-gathering system for the flying laboratory on the basis of 32-bit microcontroller 1986ВЕ1 and ADC with PLL, the parameters of which are given in table.1. ADC with PLL is a tracking system with astaticism of the second order. The steady-state error in such devices is equal to zero, more precisely – to the bias voltage at the input of op-amp +Ux / Косс, where Косс is common-mode rejection ratio (CMRR) of op-amp. For example, ОУ 140УД31АТ, which has an input bias voltage of 25 µV and CMRR more than 110 dB, guarantees the voltage conversion Ux = 5 V into pulse duration with an accuracy of less than 0.002%. The values of resistors R1 and R3 (Fig.2) must be equal to each other (±5%) to compensate input currents of op amp. The elements R2, R4, C1 and C2 do not affect the accuracy. The voltage at the output of op-amp controls the frequency and phase of VCO. Since the VCO is a second integrating element in the PLL loop, it only responds to the steady component of this complex signal. The output signal of PD, a rectangular pulse, whose area (the average voltage value over the period of the conversion frequency F1) is equal to the input voltage Ux, is a feedback signal in the ADC circuit. PD is manufactured on the base of 5503 gate array family. The duration of the output pulse of PD can be less than 1 ns. The resolution of the ADC with PLL is determined by the performance (circuitry) of the circuit of PD and by a clock frequency of MC or counter, which forms a signal F1. The maximum operating frequencies of MC and logic elements had reached the level of 1 GHz and above. It is important to note the great potential of ADC with PLL. Moreover, the device contains only one precision element – operational amplifier (op amp). Other elements (resistors and capacitors) may have uncertainty of ± (5–10)%. Possibilities of ADC with PLL based on a 32-bit 1986ВЕ1Т microcontroller with a clock frequency of 140 MHz are tested and presented in table.2. In 2015, to reduce the dimensions of the designed ADC with a PLL, SMC "Technological Centre" has developed and manufactured the 5503ХМ1У-651 chip of dual-channel PLL. The chip has 28 pins, supply voltage of 5 V and is made using 1.6 µm CMOS technology. Fig.3 shows the 5503ХМ1У-651 chip in MK 5123.28-1.01 package. One 5503ХМ1У-651 chip replaces more than 30 standard logic chips on discrete components, which are used to build components of the PLL. The chip includes the phase detector and VCO. SMC "Technological Centre" has developed a gate array family with standardized library of basic and standard functional cells, common design tool based on Kovcheg CAD and the means for prototyping . The entry-level 5503 and 5507 gate array families have uniform nomenclature and are based on radiation-hardened 1.6 µm bulk silicon CMOS technology. Wiring is carried out in the first metal layer and in the polysilicon layer. Gate arrays of these series are allowed for use in special-purpose equipment . More than 600 types of semicustom very large scale integrated circuits of various purpose are designed and manufactured on the basis of 5503 and 5507 gate arrays families, including for space-based equipment, for example, for Progress-M and Soyuz-TMA spacecrafts, Briz-M upper stages and many other [6,7,8]. The 5503ХМ1У-653 chip with two additional 4-bit counters has been created on the basis of 5503ХМ1У-651 chip. The counter divides the output frequency of the VCO by 16, thereby averaging the noise of the VCO and, consequently, reducing ADC noise. 5503ХМ1У-617 chip, containing a set of op amps, was used to implement the low-pass filter. Fig.4 shows a block diagram of one channel of the PLL using 5503ХМ1У-653 and 5503ХМ1У-617 chips. 55503ХМ1У-617 chip includes the following functional blocks (Fig.5): • six independent op-amps; • two inverting amplifier; • reference voltage source (1,12 V); • current setting unit. The current setting unit for setting of op-amp mode is connected to the R0 pin. Between this pin and "total 0V" it is necessary to connect a resistor from 100 kΩ to 1 MΩ to set the bias current of all op-amps, which determines their performance. The total consumption current of IC is proportional to the current through the R0 output. The reference voltage source on width of forbidden band has a high resistance CREF output to connect a filter capacitor (about 10 nF) and the input for INRI mode. The change of voltage on the CREF output in the temperature range is depended by the value of external adjustment resistor on the INRI output. Between this output and the "total 0" it is necessary to connect a resistor – from 8.1 kΩ to 10 kΩ. The sensitivity of the reference voltage source to the change in voltage is 2 mV/V. Inside the chip the CREF output is connected to the noninverting inputs of the op-amp. The characteristics of a single op-amp are presented in table.3. The development of the circuitry for implementation of the ADC with PLL continues. SMC "Technological Centre" has developed on the basis of the 5503ХМ1У-653 chip the 5503ХМ1У-670 chip. The new chip includes additional operational amplifier for implementation of low-pass filter, and also modified VCO. ■
This paper was created with the financial support of the Ministry of Education and Science of the Russian Federation. Unique identifier RFMEFI58015X0005.