rus
Issue #5/2015
V.Verner, E.Kuznetsov, A.Saurov
Fiftieth anniversary of Moore’s Law: Development of micro- and nanoElectronics
Fiftieth anniversary of Moore’s Law: Development of micro- and nanoElectronics
The second part of the article examines how Moore’s Law influenced the development of micro- and nanoelectronics, and what changes it caused in the structure of the industry. It is noted, that Moore’s Law greatly influenced the development of semiconductor electronics by setting high growth rate of microelectronics. Subsequently, it contributed to the emergence and development of new areas, for example, MEMS and nanoelectronics.
Теги: integrated device manufacturing internet of things mems micro- and nanoelectronics интегрированное производство интернет вещей микронаноэлектроника мэмс
Moore’s Law greatly influenced the development of semiconductor electronics by setting high growth rate of its most important component – microelectronics. Subsequently, it contributed to the emergence and development of new areas, for example, microsystem technology in the form of MEMS and nanoelectronics. As a result, electronics has become the leading sector, largely determining the development of the world economy as a whole (fig.1).
According to the SEMI, the market of microelectronics definitively went over 300 billion USD in 2013 [2]. However, new characteristic dimensions are developing more slowly (fig.2) [3].
Despite financial difficulties, microelectronics remains a highly knowledge-intensive industry and the R&D capital expenditures are comparable to or even higher than the capital expenditures of production. In 1970–80s, the capital expenditures were 7–8% of the profits, growing steadily and peaking at 17.5% [4] in 2008. Currently, they are falling back to 5–7% [5]. However, these are average figures. The leaders enjoy large growth, which may be not steady, though, and which depends on the company’s policy in the field of R&D [4].
Various forms of companies’ collective participation in this process plays a significant role in the development of the scientific basis for the manufacture of ICs. At the initial stage of microelectronics development, they focused on resolving the problems of integrated device manufacturing (IDM) of ICs. The structural change of the IC manufacture, i. e. emergence of new forms of specialization – foundry-fabless – in addition to IDM, has resulted in counter-trends. The IDM companies commenced using some foundry-fabless elements, and the latter commenced arranging systems similar to IDM [6].
New consortia started including the manufacture of ICs, production of equipment and materials, development of CAD. System companies are also expected to be included therein [7]. According to the author of [8], research has always been in the DNA of microelectronics. Only a small number of other industries have the same level of contributions to the science from the profits. At the same time, the driving force of this research was Moore’s Law, which was defined by the mantra that said "cheaper, better, faster, smaller" [8]. Martin van den Brink, the president of ASML, has the same opinion, believing that it is very unproductive to discuss the end of Moore’s Law, because it is an extrapolation of the past, in fact: there is no Moore’s Law, but there are a lot of smart people in the electronics industry [9].
Ludo Deferm, the Vice-President of IMEC [10], noted that the semiconductor industry had developed following Moore’s Law for almost 50 years, but can this law continue to sustain the development? New technologies (EUV, transition to 450 mm), may indeed lead to a lower price of the transistor, but the initial equipment costs are very high, and it is unknown how they will be compensated. One of the possibilities for reducing the initial costs is wide development of cooperation, for which the next few years are believed to be critical because the level of cooperation between industrial, research and governmental organizations of different levels will determine the growth rate. Moore’s Law established general development pace for the industry. Perhaps, in certain areas, for example, in 3D integration, there will be some new criteria of development, a sort of "local" Moore’s Law.
If earlier the leading companies excelled primarily in production volumes, at the new microelectronics development stage they became owners of more advanced designs and technologies, such as, Intel’s FinFET, for example. Essentially, a large number of branded competing technologies have emerged, and their choice depends to some extent on the company’s share on the market.
Companies with large volumes of mass production are focusing on a transition to 450 mm wafers and EUV lithography. Companies with small and medium production volumes are considering other various lithography technologies, including the continued use of sub-wavelength immersion lithography of 193 nm using multiple patterning and new technologies of direct self-assembly (DSA). Another option could maskless litography (ML2) using matrices of laser or electron beams [11].
Research, design and production organizations are undergoing significant transformation with the development of microelectronics [12]. New devices are developed and existing designs are used more efficiently. In general, the microelectronic ecosystem is rapidly growing by incorporating various associations and companies [13–15].
In 2012, it was suggested that only five companies would be able to produce 15 nm ICs [5], but the 2014 data reveal that the number of companies working with the 14/16 nm standards was seven in 2013, twenty-six in 2014, and it is expected to reach thirty-three in 2015 [6]. In 2013, twenty-six factories worked with the 25/19 nm standards and twenty-six enterprises with the 32/28 nm standards [3].
Both structural and technological changes in microelectronics are accompanied by a general growth of the semiconductor industry. SEMI notes that the average growth of capital investments in equipment was 20–30% in 2014 [17]. Investments are aimed at the development of projects for construction and equipment of production lines for different areas of the semiconductor industry (190 projects in 2014, and 250 in 2015) [6].
Apart from general trends, Moore’s Law has a less obvious effect on some areas of the semiconductor industry development, promoting competition among leading companies.
The strongest advocate of applying Moore’s Law until the characteristic dimension (N-node) reaches 7–5 nm is Intel [18]. To some extent, this is due to Intel’s transition to the foundry model as it was announced in November 2013. However, some other preconditions are required to provide competitive advantage, above all, vis-а-vis TSMC [19]. In this regard, Intel refers to its leadership in the technology.
Intel was on average 3.5 years ahead of its competitors (TSMC, GlobalFoundries, Samsung, IBM) with its High-K dielectrics, use of SiGe strained silicon, HKMG and Tri-Gate [18, 19]. Yet, substantial advantage can be provided by a price reduction of IC transistors with the transition to smaller characteristic dimensions. Until 28 nm, the price is known to drop by approximately 30% at each cycle.
Fig.4, which supposedly demonstrates Intel’s progress according to Moore’s Law, reflects the corresponding developmental vectors [18]. The linear graph (Fig.4a) of transistor price reduction during the transition from 65 nm to 10 nm shows a 20% price decrease per cycle. It is less than the above-said 30%, but still the price is declining, indeed. It should be noted that many critics find this fact questionable because they see no reason for reducing the cost of production currently, and in the future given the rising prices of equipment. Furthermore, the technical characteristics change more slowly than suggested by Moore’s Law. Thus, in embedded SRAMs, the cell area is 0.09 μm2 when the characteristic dimensions are 22–20 nm, and in case of 11–10 nm, the cell area will decrease to 0.06 μm 2, or only 30% instead of a four times reduction (0.02 μm2) stipulated by the geometric scaling rule of Moore’s Law [20].
In [21], it is noted that regarding the gate cost, which is the main market indicator, FinFET is inferior to the bulk CMOS because the FinFET price is higher in the interval from 2015 to 2017, and the rate of annual price decline in case of launching the production is lower. The area of FinFET is top-level high-density electronic equipment. For the mass market, FinFET ICs are price ineffective. H. Jones, an analyst from IBS, explains: "FinFET is not the best silicon path" [21].
FinFET and FD-SOI have a particular important competition in the field of fully depleting ICs. ICs on SOI seem to have little chance to compete with other technologies, because the cost of unprocessed SOI wafers is significantly higher than the cost of bulk ICs wafers (500 USD vs. 120 USD) [22]. But because of the SOI technology simplicity, the cost of processed SOI wafers is comparable to the cost of conventional bulk Si ICs and is significantly lower than the FinFET wafer price, because the cost of FinFET technological operations is significantly higher having the same FD-SOI functionality.
The cost of processed 14 nm FD-SOI wafers is 18.4% lower than the cost of 16 nm FinFET wafers. The benefits of FD-SOI are believed to make this technology widely used in various electronics fields for the next 10 years. The proximity of the FD-SOI to the well-developed planar CMOS technology makes both design and manufacture cheap. It is very important that FD-SOI can be easily integrated in a variety of 3D technologies.
From the perspective of the discussed IC price issue, a visual representation of correlation between the prices of bulk Si CMOS, FinFET and FD-SOI is given in Fig.5, from which it is clear that the cost of the FD-SOI chip (100 mm2) with the characteristic dimensions of 28 nm, 20 nm and 14/16 nm is always lower than the competitor’s cost. Naturally, the price of the FD-SOI wafer is also lower than the competitor’s price (fig.6).
From these facts, it is clear that FD-SOI is used to create ICs with the same characteristic dimensions as FinFET. The proximity to the conventional planar technology ensures that FD-SOI can be used to design and to create ICs with a lower cost than FinFET. Thus, FD-SOI is significantly more affordable than FinFET, but, in contrast to the well-developed ecosystem of the latter, the ecosystem of the former is only emerging.
It should be noted that FinFET and FD-SOI supporters believe that the development of microelectronics is occurring as the result of Moore’s Law, albeit in a truncated form. An example of this can be the message about the presentation of STMicroelectronics at ISS Europe Symposium [23]. Fig.7 shows one of the slides of the presentation.
The axes of Price and Functionality divide the graph into four zones. In fact, the graph is not about the main ratios of the law, but is about relative changes in the characteristics of ICs occurring during the transition to the next cycle. For example, the cost increases by 10 percent and the functionality increases by 30 percent, or only the functionality increases, or the price and the functionality increases equally. Note that Moore’s Law never refers to any reduction of price. Thus, both in the above-discussed FinFET case and in the FD-SOI case, Moore’s Law is not about quantity, but is about qualitative directions of microelectronics development. This trend is highlighted in [22], where it was stated: "1 gain node without scaling", i. e. a new characteristic node is achieved without scaling.
Probably, another important aspect is combining 3D architecture with low power consumption, which is referred to as a new era of scaling: "3D power scaling". An increase in the number of transistors per area unit is accompanied by an increase in the number of transistor layers in the vertical direction [24]. The density (integration) increases without reducing individual 2D-dimensions. As a result, 3D structures have parameters comparable with the typical N+1 2D-scaling when the sizes equal N or even N-1 [25]. It is clear that this can improve the cost.
Transition to 3D structures is discussed as one of possible ways for microelectronics development, as a "New Paradigm – Scaling System through 3D system integration" [26]. One of the drivers was the problem of signal delay in the interconnections of ICs. For N16, the delay in interconnections is almost 1000 times longer than in transistors [27]. This factor combined with increasing prices of further 2D scaling necessitates a transition to 3D integration.
TSV-based stack technology partially resolves the problem of interconnections. However, it is better resolved using monolithic 3D-structures (M3D). The M3D structures began to be developed by Qualcomm [28] and the research center CEA-LETI [25, 28]. These structures allow some scaling according to an updated version of Moore’s Law [28].
The stack 3D ICs developers believe that this area will greatly contribute to the development of nanoelectronic systems [29, 30]. They believe that Moore’s Law is not over – it is just slowing. Examples of effective stack 3D ICs are IC memories Hybrid Memory Cube (HMC) and 3D NAND manufactured by Micron.
In reality, it is not so simple. Firstly, the process of transition to 3D ICs may be rather long. Secondly, it requires some additional equipment and clean rooms. As a result, according to experts from Micron, this transition may be twice as expensive as the transition to 20 nm. In addition, the dimensions of the 3D NAND are still greater than the dimensions of 2D alternatives [3].
Lowering production cost and searching for new consumers are persistent problems, with customers often agreeing to a reduction of price, even at the expense of some deterioration in the quality characteristics of ICs. The price reduction can be achieved in different ways [26]:
decrease in the cost of individual processes in the transition to new technological cycles. IMEC in collaboration with Alix Partners are working in this direction for 10–7 nm [31];
transition to a new lithography (EUV), because when using multiple exposures based on 193 nm lithography for the next technological cycle, it is necessary to increase the number of masking stages by 15–20%, which accordingly makes the process more expensive;
use of 450 mm wafers. A periodic increase in the wafer diameter in order to reduce the crystal price is one of the consequences of Moore’s Law. Note that the EUV and transition to 450 mm wafers are technically feasible in the manufacture [32], but the high cost of implementation may shift the beginning of their commercial use to a later time [33]. The pilot production was almost complete on the experimental site in Albany (USA) under the assistance of Intel, TSMC, Samsung, IBM, GlobalFoundries (GF) as early as the end of 2013 [32]. The need for new generation of computer chips can be considered as a fact, so the transition to new lithography and new wafers is inevitable [34];
the rapid development of mobile/wearable technology has led to an increased demand for ECB, to which performance requirements are not as high as for high-level computational tools. Therefore, the function price may be reduced [35];
development of 3D ECB, where the function price, as we have noted, may be reduced. It reflects the trend of components transition to a system level. In this case, the third dimension is used for increased functionality in addition to the conventional 2D miniaturization. 3D technologies in different embodiments use the connection of both homogeneous and heterogeneous layers vertically. Layer thickness and number may become new scaling factors, and the integration degree may be determined not relative to an area unit, but relative to a volume unit. The increase in the degree of volumetric integration may lead to reduction of cost per unit of functionality, for example per bit of information. Thus, there is a qualitative analogy with Moore’s Law, which leads to discussion of its new trajectory [36].
Deviations from Moore’s Law have resulted, above all, in the breach of the triad "smaller, faster, cheaper". The domain "More Moore" (MM) has practically reduced to an integration growth happening every two or more years (see Table).
The rising production cost has resulted in practical termination of the simultaneous price reduction. According to the President of Imec, Luc van den Hove [37], the driving force has not been the price reduction of the key (transistor), but the price reduction of the function. This has led to an increasing role of other domains in semiconductor manufacture. The significant commercial success of MEMS manufacture has resulted in the emergence of the "MEMS White Book" ITRS [38], but the real success may be achieved only with mass production.
The number of "More than Moore" (MTM) domain products is already close to that number in the MM domain [39], and is even ahead of it according to such an important indicator as reduction of the price/functionality ratio [40]. The convergence of these two domains is critical. As a result, instead of a homogeneous solution, which is typical for silicon electronics of the MM domain, a transition is occurring to heterogeneous solutions of the MTM domain. This allowed the author [41] to reformulate the domain MTM name as "Moore’s Law 2.0". It is unlikely that the update sign "2.0" will be widely accepted in respect of Moore’s Law in the formulation presented on the eloquent Fig. 8, but the sign of changes in the analysis of electronic industry has become ITRS 2.0.
The first step was made in the different forms of wearable electronics, primarily, home appliances. However, the gigantic impulse was associated with the emergence of "Internet of Things’ (IOT), which was soon paraphrased as "Internet for Everything".
According to various expert companies, the 2020 IOT market can range from 1.9 trillion to 26 trillion USD [42]. This range implies an explosive growth in this type of electronics. It made ITRS reformulate their concepts for analyzing the semiconductor industry development in the form of ITRS 2.0, which deviated from the standard form of analysis adopted in 1992, where the focus was on evaluation from the standpoint of Moore’s Law [43]. Now it examines the development trends in key market sectors of semiconductors and their application, and not only at the chip level, but also at the system level. The ITRS 2.0 analysis is conducted using seven building blocks:
system integration, which focuses on the selection of architectures required by the industry and based on heterogeneous devices of some specific systems;
off-system communications based on physical and wireless technologies between parts of the system;
heterogeneous integration of individual production technologies into an aggregated product with advanced functionality;
heterogeneous components that do not require scaling according to Moore’s Law, but provide additional functionality in areas such as power control or in sensing and actuation;
"Beyond CMOS" – devices based on new physical principles and providing functional scaling beyond CMOS, for example, spin devices, ferromagnetic logic technologies, atomic keys, etc.;
"More Moore" – consistent reduction of horizontal and vertical sizes in order to reduce the cost and to improve the performance;
Integration of production through procedures and processes required for mass production at a reasonable price.
It is noteworthy that the areas of ITRS 2.0 analysis start with top-down system integration to identify trends in the product consumption market of the semiconductor industry in 2015–2030. A new system metrics need to be developed for prediction of trends in the electronics development in areas of mobile electronics, IOT and cloud infrastructure (Big Data). It is anticipated that it will replace the current conventional scaling metrics, and it will be a revolutionary change after 50 evolutional years in the framework of Moore’s Law. For our part, we note that to some extent the initial situation of microelectronics development is reiterating, when system companies determined its development trend (see part 1, table 3).
The said trends are illustrated as an example for IOT in fig. 9, which may be viewed as an option for the situation in fig. 10 (see part 1).
Significant role of IOT in the development of electronics, reflected in the new ITRS document, is well grounded because package solutions for IOT include not only individual modems or sensors, but also communication channels (mostly wireless) with cloud services based on new algorithms [44].
The big data market will require using new types of solid-state storage devices and microprocessors. Cloud and mobile technologies will require more energy-efficient memory and MEMS. The analytical company IHS believes that the leading technologies will change the world in the next 5 years. These include "Internet for Everything", big data cloud systems and 3D printing. The latter is also reasonable because there will be a need for various design solutions for IOT devices [45].
The IOT role in the development is being actively discussed in all international conferences and exhibitions of electronics, for example at "Electronics-2014" in Munich. It is noted that an obstacle in the spread of IOT may be the issue of privacy (security), which may also be resolved with special ICs and devices [46].
IOT is a communication technology of the global level, but, in the coming years, significant growth is also anticipated at the local level of communication between structures. For example, this applies to wearable devices, the development of which may occur under IOT or independently [47]. New communication technologies must have a significant impact on the selection of energy-efficient components from among devices of the same type [48] or competing devices, for example, digital or analog ICs [49]. Therefore, energy efficiency may be an additional parameter in the development of the electronics elements along with the classical triad of Moore’s Law – "smaller, faster, cheaper".
The optimistic estimate of the future development of the IOT market may be highly exaggerated. Trillions of IOT products projected for the next decade seem to be excessive against the more realistic estimates of the semiconductor industry. In [50], it is assumed that, in 2017, a trillion of semiconductor devices will be released, but the share ICs will constitute only 26%, and 74% are opto-sensor-discrete devices (OSD), which are the main products for IOT. However, from the price perspective, the picture is opposite: ICs cover 65% of the market and OSD – 35%.
In the third part of the article, we will once again discuss Moore’s Law, but from the perspective of emerging deviations that may lead to a denial of its influence on the development of micro- and nanoelectronics.
According to the SEMI, the market of microelectronics definitively went over 300 billion USD in 2013 [2]. However, new characteristic dimensions are developing more slowly (fig.2) [3].
Despite financial difficulties, microelectronics remains a highly knowledge-intensive industry and the R&D capital expenditures are comparable to or even higher than the capital expenditures of production. In 1970–80s, the capital expenditures were 7–8% of the profits, growing steadily and peaking at 17.5% [4] in 2008. Currently, they are falling back to 5–7% [5]. However, these are average figures. The leaders enjoy large growth, which may be not steady, though, and which depends on the company’s policy in the field of R&D [4].
Various forms of companies’ collective participation in this process plays a significant role in the development of the scientific basis for the manufacture of ICs. At the initial stage of microelectronics development, they focused on resolving the problems of integrated device manufacturing (IDM) of ICs. The structural change of the IC manufacture, i. e. emergence of new forms of specialization – foundry-fabless – in addition to IDM, has resulted in counter-trends. The IDM companies commenced using some foundry-fabless elements, and the latter commenced arranging systems similar to IDM [6].
New consortia started including the manufacture of ICs, production of equipment and materials, development of CAD. System companies are also expected to be included therein [7]. According to the author of [8], research has always been in the DNA of microelectronics. Only a small number of other industries have the same level of contributions to the science from the profits. At the same time, the driving force of this research was Moore’s Law, which was defined by the mantra that said "cheaper, better, faster, smaller" [8]. Martin van den Brink, the president of ASML, has the same opinion, believing that it is very unproductive to discuss the end of Moore’s Law, because it is an extrapolation of the past, in fact: there is no Moore’s Law, but there are a lot of smart people in the electronics industry [9].
Ludo Deferm, the Vice-President of IMEC [10], noted that the semiconductor industry had developed following Moore’s Law for almost 50 years, but can this law continue to sustain the development? New technologies (EUV, transition to 450 mm), may indeed lead to a lower price of the transistor, but the initial equipment costs are very high, and it is unknown how they will be compensated. One of the possibilities for reducing the initial costs is wide development of cooperation, for which the next few years are believed to be critical because the level of cooperation between industrial, research and governmental organizations of different levels will determine the growth rate. Moore’s Law established general development pace for the industry. Perhaps, in certain areas, for example, in 3D integration, there will be some new criteria of development, a sort of "local" Moore’s Law.
If earlier the leading companies excelled primarily in production volumes, at the new microelectronics development stage they became owners of more advanced designs and technologies, such as, Intel’s FinFET, for example. Essentially, a large number of branded competing technologies have emerged, and their choice depends to some extent on the company’s share on the market.
Companies with large volumes of mass production are focusing on a transition to 450 mm wafers and EUV lithography. Companies with small and medium production volumes are considering other various lithography technologies, including the continued use of sub-wavelength immersion lithography of 193 nm using multiple patterning and new technologies of direct self-assembly (DSA). Another option could maskless litography (ML2) using matrices of laser or electron beams [11].
Research, design and production organizations are undergoing significant transformation with the development of microelectronics [12]. New devices are developed and existing designs are used more efficiently. In general, the microelectronic ecosystem is rapidly growing by incorporating various associations and companies [13–15].
In 2012, it was suggested that only five companies would be able to produce 15 nm ICs [5], but the 2014 data reveal that the number of companies working with the 14/16 nm standards was seven in 2013, twenty-six in 2014, and it is expected to reach thirty-three in 2015 [6]. In 2013, twenty-six factories worked with the 25/19 nm standards and twenty-six enterprises with the 32/28 nm standards [3].
Both structural and technological changes in microelectronics are accompanied by a general growth of the semiconductor industry. SEMI notes that the average growth of capital investments in equipment was 20–30% in 2014 [17]. Investments are aimed at the development of projects for construction and equipment of production lines for different areas of the semiconductor industry (190 projects in 2014, and 250 in 2015) [6].
Apart from general trends, Moore’s Law has a less obvious effect on some areas of the semiconductor industry development, promoting competition among leading companies.
The strongest advocate of applying Moore’s Law until the characteristic dimension (N-node) reaches 7–5 nm is Intel [18]. To some extent, this is due to Intel’s transition to the foundry model as it was announced in November 2013. However, some other preconditions are required to provide competitive advantage, above all, vis-а-vis TSMC [19]. In this regard, Intel refers to its leadership in the technology.
Intel was on average 3.5 years ahead of its competitors (TSMC, GlobalFoundries, Samsung, IBM) with its High-K dielectrics, use of SiGe strained silicon, HKMG and Tri-Gate [18, 19]. Yet, substantial advantage can be provided by a price reduction of IC transistors with the transition to smaller characteristic dimensions. Until 28 nm, the price is known to drop by approximately 30% at each cycle.
Fig.4, which supposedly demonstrates Intel’s progress according to Moore’s Law, reflects the corresponding developmental vectors [18]. The linear graph (Fig.4a) of transistor price reduction during the transition from 65 nm to 10 nm shows a 20% price decrease per cycle. It is less than the above-said 30%, but still the price is declining, indeed. It should be noted that many critics find this fact questionable because they see no reason for reducing the cost of production currently, and in the future given the rising prices of equipment. Furthermore, the technical characteristics change more slowly than suggested by Moore’s Law. Thus, in embedded SRAMs, the cell area is 0.09 μm2 when the characteristic dimensions are 22–20 nm, and in case of 11–10 nm, the cell area will decrease to 0.06 μm 2, or only 30% instead of a four times reduction (0.02 μm2) stipulated by the geometric scaling rule of Moore’s Law [20].
In [21], it is noted that regarding the gate cost, which is the main market indicator, FinFET is inferior to the bulk CMOS because the FinFET price is higher in the interval from 2015 to 2017, and the rate of annual price decline in case of launching the production is lower. The area of FinFET is top-level high-density electronic equipment. For the mass market, FinFET ICs are price ineffective. H. Jones, an analyst from IBS, explains: "FinFET is not the best silicon path" [21].
FinFET and FD-SOI have a particular important competition in the field of fully depleting ICs. ICs on SOI seem to have little chance to compete with other technologies, because the cost of unprocessed SOI wafers is significantly higher than the cost of bulk ICs wafers (500 USD vs. 120 USD) [22]. But because of the SOI technology simplicity, the cost of processed SOI wafers is comparable to the cost of conventional bulk Si ICs and is significantly lower than the FinFET wafer price, because the cost of FinFET technological operations is significantly higher having the same FD-SOI functionality.
The cost of processed 14 nm FD-SOI wafers is 18.4% lower than the cost of 16 nm FinFET wafers. The benefits of FD-SOI are believed to make this technology widely used in various electronics fields for the next 10 years. The proximity of the FD-SOI to the well-developed planar CMOS technology makes both design and manufacture cheap. It is very important that FD-SOI can be easily integrated in a variety of 3D technologies.
From the perspective of the discussed IC price issue, a visual representation of correlation between the prices of bulk Si CMOS, FinFET and FD-SOI is given in Fig.5, from which it is clear that the cost of the FD-SOI chip (100 mm2) with the characteristic dimensions of 28 nm, 20 nm and 14/16 nm is always lower than the competitor’s cost. Naturally, the price of the FD-SOI wafer is also lower than the competitor’s price (fig.6).
From these facts, it is clear that FD-SOI is used to create ICs with the same characteristic dimensions as FinFET. The proximity to the conventional planar technology ensures that FD-SOI can be used to design and to create ICs with a lower cost than FinFET. Thus, FD-SOI is significantly more affordable than FinFET, but, in contrast to the well-developed ecosystem of the latter, the ecosystem of the former is only emerging.
It should be noted that FinFET and FD-SOI supporters believe that the development of microelectronics is occurring as the result of Moore’s Law, albeit in a truncated form. An example of this can be the message about the presentation of STMicroelectronics at ISS Europe Symposium [23]. Fig.7 shows one of the slides of the presentation.
The axes of Price and Functionality divide the graph into four zones. In fact, the graph is not about the main ratios of the law, but is about relative changes in the characteristics of ICs occurring during the transition to the next cycle. For example, the cost increases by 10 percent and the functionality increases by 30 percent, or only the functionality increases, or the price and the functionality increases equally. Note that Moore’s Law never refers to any reduction of price. Thus, both in the above-discussed FinFET case and in the FD-SOI case, Moore’s Law is not about quantity, but is about qualitative directions of microelectronics development. This trend is highlighted in [22], where it was stated: "1 gain node without scaling", i. e. a new characteristic node is achieved without scaling.
Probably, another important aspect is combining 3D architecture with low power consumption, which is referred to as a new era of scaling: "3D power scaling". An increase in the number of transistors per area unit is accompanied by an increase in the number of transistor layers in the vertical direction [24]. The density (integration) increases without reducing individual 2D-dimensions. As a result, 3D structures have parameters comparable with the typical N+1 2D-scaling when the sizes equal N or even N-1 [25]. It is clear that this can improve the cost.
Transition to 3D structures is discussed as one of possible ways for microelectronics development, as a "New Paradigm – Scaling System through 3D system integration" [26]. One of the drivers was the problem of signal delay in the interconnections of ICs. For N16, the delay in interconnections is almost 1000 times longer than in transistors [27]. This factor combined with increasing prices of further 2D scaling necessitates a transition to 3D integration.
TSV-based stack technology partially resolves the problem of interconnections. However, it is better resolved using monolithic 3D-structures (M3D). The M3D structures began to be developed by Qualcomm [28] and the research center CEA-LETI [25, 28]. These structures allow some scaling according to an updated version of Moore’s Law [28].
The stack 3D ICs developers believe that this area will greatly contribute to the development of nanoelectronic systems [29, 30]. They believe that Moore’s Law is not over – it is just slowing. Examples of effective stack 3D ICs are IC memories Hybrid Memory Cube (HMC) and 3D NAND manufactured by Micron.
In reality, it is not so simple. Firstly, the process of transition to 3D ICs may be rather long. Secondly, it requires some additional equipment and clean rooms. As a result, according to experts from Micron, this transition may be twice as expensive as the transition to 20 nm. In addition, the dimensions of the 3D NAND are still greater than the dimensions of 2D alternatives [3].
Lowering production cost and searching for new consumers are persistent problems, with customers often agreeing to a reduction of price, even at the expense of some deterioration in the quality characteristics of ICs. The price reduction can be achieved in different ways [26]:
decrease in the cost of individual processes in the transition to new technological cycles. IMEC in collaboration with Alix Partners are working in this direction for 10–7 nm [31];
transition to a new lithography (EUV), because when using multiple exposures based on 193 nm lithography for the next technological cycle, it is necessary to increase the number of masking stages by 15–20%, which accordingly makes the process more expensive;
use of 450 mm wafers. A periodic increase in the wafer diameter in order to reduce the crystal price is one of the consequences of Moore’s Law. Note that the EUV and transition to 450 mm wafers are technically feasible in the manufacture [32], but the high cost of implementation may shift the beginning of their commercial use to a later time [33]. The pilot production was almost complete on the experimental site in Albany (USA) under the assistance of Intel, TSMC, Samsung, IBM, GlobalFoundries (GF) as early as the end of 2013 [32]. The need for new generation of computer chips can be considered as a fact, so the transition to new lithography and new wafers is inevitable [34];
the rapid development of mobile/wearable technology has led to an increased demand for ECB, to which performance requirements are not as high as for high-level computational tools. Therefore, the function price may be reduced [35];
development of 3D ECB, where the function price, as we have noted, may be reduced. It reflects the trend of components transition to a system level. In this case, the third dimension is used for increased functionality in addition to the conventional 2D miniaturization. 3D technologies in different embodiments use the connection of both homogeneous and heterogeneous layers vertically. Layer thickness and number may become new scaling factors, and the integration degree may be determined not relative to an area unit, but relative to a volume unit. The increase in the degree of volumetric integration may lead to reduction of cost per unit of functionality, for example per bit of information. Thus, there is a qualitative analogy with Moore’s Law, which leads to discussion of its new trajectory [36].
Deviations from Moore’s Law have resulted, above all, in the breach of the triad "smaller, faster, cheaper". The domain "More Moore" (MM) has practically reduced to an integration growth happening every two or more years (see Table).
The rising production cost has resulted in practical termination of the simultaneous price reduction. According to the President of Imec, Luc van den Hove [37], the driving force has not been the price reduction of the key (transistor), but the price reduction of the function. This has led to an increasing role of other domains in semiconductor manufacture. The significant commercial success of MEMS manufacture has resulted in the emergence of the "MEMS White Book" ITRS [38], but the real success may be achieved only with mass production.
The number of "More than Moore" (MTM) domain products is already close to that number in the MM domain [39], and is even ahead of it according to such an important indicator as reduction of the price/functionality ratio [40]. The convergence of these two domains is critical. As a result, instead of a homogeneous solution, which is typical for silicon electronics of the MM domain, a transition is occurring to heterogeneous solutions of the MTM domain. This allowed the author [41] to reformulate the domain MTM name as "Moore’s Law 2.0". It is unlikely that the update sign "2.0" will be widely accepted in respect of Moore’s Law in the formulation presented on the eloquent Fig. 8, but the sign of changes in the analysis of electronic industry has become ITRS 2.0.
The first step was made in the different forms of wearable electronics, primarily, home appliances. However, the gigantic impulse was associated with the emergence of "Internet of Things’ (IOT), which was soon paraphrased as "Internet for Everything".
According to various expert companies, the 2020 IOT market can range from 1.9 trillion to 26 trillion USD [42]. This range implies an explosive growth in this type of electronics. It made ITRS reformulate their concepts for analyzing the semiconductor industry development in the form of ITRS 2.0, which deviated from the standard form of analysis adopted in 1992, where the focus was on evaluation from the standpoint of Moore’s Law [43]. Now it examines the development trends in key market sectors of semiconductors and their application, and not only at the chip level, but also at the system level. The ITRS 2.0 analysis is conducted using seven building blocks:
system integration, which focuses on the selection of architectures required by the industry and based on heterogeneous devices of some specific systems;
off-system communications based on physical and wireless technologies between parts of the system;
heterogeneous integration of individual production technologies into an aggregated product with advanced functionality;
heterogeneous components that do not require scaling according to Moore’s Law, but provide additional functionality in areas such as power control or in sensing and actuation;
"Beyond CMOS" – devices based on new physical principles and providing functional scaling beyond CMOS, for example, spin devices, ferromagnetic logic technologies, atomic keys, etc.;
"More Moore" – consistent reduction of horizontal and vertical sizes in order to reduce the cost and to improve the performance;
Integration of production through procedures and processes required for mass production at a reasonable price.
It is noteworthy that the areas of ITRS 2.0 analysis start with top-down system integration to identify trends in the product consumption market of the semiconductor industry in 2015–2030. A new system metrics need to be developed for prediction of trends in the electronics development in areas of mobile electronics, IOT and cloud infrastructure (Big Data). It is anticipated that it will replace the current conventional scaling metrics, and it will be a revolutionary change after 50 evolutional years in the framework of Moore’s Law. For our part, we note that to some extent the initial situation of microelectronics development is reiterating, when system companies determined its development trend (see part 1, table 3).
The said trends are illustrated as an example for IOT in fig. 9, which may be viewed as an option for the situation in fig. 10 (see part 1).
Significant role of IOT in the development of electronics, reflected in the new ITRS document, is well grounded because package solutions for IOT include not only individual modems or sensors, but also communication channels (mostly wireless) with cloud services based on new algorithms [44].
The big data market will require using new types of solid-state storage devices and microprocessors. Cloud and mobile technologies will require more energy-efficient memory and MEMS. The analytical company IHS believes that the leading technologies will change the world in the next 5 years. These include "Internet for Everything", big data cloud systems and 3D printing. The latter is also reasonable because there will be a need for various design solutions for IOT devices [45].
The IOT role in the development is being actively discussed in all international conferences and exhibitions of electronics, for example at "Electronics-2014" in Munich. It is noted that an obstacle in the spread of IOT may be the issue of privacy (security), which may also be resolved with special ICs and devices [46].
IOT is a communication technology of the global level, but, in the coming years, significant growth is also anticipated at the local level of communication between structures. For example, this applies to wearable devices, the development of which may occur under IOT or independently [47]. New communication technologies must have a significant impact on the selection of energy-efficient components from among devices of the same type [48] or competing devices, for example, digital or analog ICs [49]. Therefore, energy efficiency may be an additional parameter in the development of the electronics elements along with the classical triad of Moore’s Law – "smaller, faster, cheaper".
The optimistic estimate of the future development of the IOT market may be highly exaggerated. Trillions of IOT products projected for the next decade seem to be excessive against the more realistic estimates of the semiconductor industry. In [50], it is assumed that, in 2017, a trillion of semiconductor devices will be released, but the share ICs will constitute only 26%, and 74% are opto-sensor-discrete devices (OSD), which are the main products for IOT. However, from the price perspective, the picture is opposite: ICs cover 65% of the market and OSD – 35%.
In the third part of the article, we will once again discuss Moore’s Law, but from the perspective of emerging deviations that may lead to a denial of its influence on the development of micro- and nanoelectronics.
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