3D CMOS, memristor nanotechnology for creating logical and memory matrices of neuroprocessor
Currently, neuromorphic CMOS devices are being developed. For example, the IBM TrueNorth  processor, thanks to the multi-core architecture, provides sufficient performance for modeling the cortical column of the brain. Integration of a memristor crossbar with CMOS transistor logic is already used in the development of a hardware neuromorphic network  and the production of a planar logic matrix .
The integration of CMOS transistors and memristors, implemented in a multilayer 3D topology, creates the prerequisites for the creation of electronic circuits with new capabilities inherent in neuromorphic electronic systems and neuroprocessors. In such devices, memristors can play the role of synapses – configuration switches of logic circuits that form the logic of the entire device by programmable layer-by-layer connection of logical blocks located at different levels of a 3D matrix arranged like a cortical column of the brain. In addition, the monolithic 3D integration of configuration memory and logic circuits on memristors can significantly improve the performance and energy efficiency of configurable computing systems.
CIRCUIT DIAGRAMS OF MATRICES
The elementary cell of the multilayered logical matrix (Fig.1) differs from the planar logical matrix described in : the cell has eight inputs I1-I8, commutated through memristors M1-M8, which realize the logical functions when the inverters operate at voltages below the tunnel breakdown voltage. At voltages above tunnel breakdown, a series-connected Zener diode allows to program the memristor with an over-threshold voltage, conducting current in both directions. The load capacity of a CMOS inverter allows up to six open memristors to be used simultaneously. Considering that in programming the maximum number of outputs of the decoder of the switching device is determined by the number 2n, where n = 1, 2, 3..., the minimum number of memristors per inverter is eight.
The memristors are connected to the connected gates of the field-effect transistors T1 and T2, which are complementary connected in a manner of a CMOS-inverter. The input of the inverter is connected to the conductor P1, which leads to the periphery of the matrix, and each cell has its own conductor not connected to other cells, which is a programming circuit of memristors. The adjacent elementary cells of the same level are connected to the power lines Vdd and Vss, through which the operating modes of the device are controlled. The supply voltage is controlled by the drivers connected to the input buses, which are placed on the periphery of the matrix.
The electrical circuit of the unit cell of the multilayer memory matrix is structurally identical to the cell of the multilayer logic matrix, but contains a larger number of memristors. The main difference of the memory matrix consisting of such cells from the logical matrix lies in the method of connecting cells to each other, which ensures selective recording and reading of individual memristors. It should be noted that the cell of the multilayer memory matrix is fundamentally different from the unit cell of the planar memory matrix  built on complementary memristors and a Zener diode. The absence of transistors in a passive planar memory matrix limits its possible size. To overcome these limitations, an active element – an inverter on two transistors – is built into the cells of the multilayer memory matrix.
A multi-layered logical matrix consisting of CMOS inverters and memristors, in the basic operation mode, implements a Boolean function built on the basis of conjunctive multi-input logic with negation of the AND-NOT type, which was previously switched by the memristor switches in the training mode. Operation AND is performed in the memristor crossbar, and the operation NOT is performed by the inverter located behind it. In a multilayer matrix, the cells are clustered. The cluster contains as many cells as there are inputs in one cell (Fig.1). The circuit diagram of a cluster of three cells based on inverters DD4–DD6 is shown in Fig.2. The inverters DD1–DD3 are part of another cluster located in the adjacent layer.
Programming memristors M1–M9 is carried out on the buses P1–P3, which are conductors of the memristor crossbar and are connected to the inputs of the corresponding inverters DD4–DD6. Voltage is applied to opposite contacts of memristors from inverters DD1–DD3. The problem of interaction during the programming of memristors is solved by control algorithm of the driver located on the periphery of the chip.
The circuit diagram of the memory matrix (Fig.3) forms a memristor crossbar consisting of 64 elementary cells (8 Ч 8 memristors). The output inverters in the figure (outputs Y) are physically located inside the cells. The inverter of each cell serves eight memristors of its cell and 56 memristors from other cells, united by a common vertical bus. For the convenience of analyzing the operation of the matrix, inverters are shown on the periphery of the circuit diagram. The change in the state of the memristors is performed by supplying to the respective horizontal and vertical buses a potential difference exceeding the threshold for the opening of memristors. The status is read line-by-line: the input inverter X of the required line supplies voltage to the horizontal bus, the other inverters at this time are in the opposite state. The state of the outputs Y in this case will be inverted with respect to the memristors state in the selected line.
To test the operation of the 3D logic matrix, a SPICE simulation of a fragment consisting of two layers, each of which contains two logical cells, was carried out. Each cell of the fragment contains two commutating memristors. Information was recorded in memristors serially. Memristors M1 and M5 have received high resistance, while the rest – low. As a result, the logical functions Y11 = V (Ч111) = X1 V X2 and Y12 = V (Ч112) = X2 were realized on the upper layer, and on the lower layer: Y21 = NOT(Y11) = NOT(X1 V X2) and Y22 = NOT(Y12) = NOT(X2).
Fig.4 shows the input and output levels of the matrix voltage obtained during the simulation. It follows from the figure that the matrix output signals obtained during the simulation correspond to the programmed functions: the signal Y11 reflects the disjunction X1 and X2, and Y12 – the inverse X2. The output signals Y21, Y22 are gated by pulses arriving at the power supply of the output inverters.
TOPOLOGY AND TECHNOLOGY
The main stages of creating a logical 3D matrix are performed using existing industrial technologies: lithography, magnetron sputtering, ion implantation, thermal diffusion and plasma etching.
First, n-MOS and p-MOS transistors with integrated gates and sinks are created in the monocrystalline silicon layer using standard CMOS technology. Then, by vacuum magnetron sputtering, the lower part of the conductors of the power lines Vss and Vdd are made. The resulting inverter is closed with a dielectric layer with a metal well that connects the signal conductor to the gates of the transistors. On top of the dielectric layer, the upper part of the power lines and eight signal conductors Iy1–Iy8 are deposited, which pass through the matrix in parallel and exit to the periphery. They are the bottom conductors of the memristor crossbar, one of which is connected to the combined gates of the transistors and serves as the input of the inverter. The free space between the conductors is filled with a dielectric. Directly on these eight conductors, a memristor layer is deposited by magnetron using the previously described technology , where vertically oriented Zener diodes D1–D8 are manufactured using a mask and the technology given in . The anode of the diode is made by growing a silicon layer and its subsequent low-temperature doping with a p-impurity by solid phase epitaxy. The cathode doped with the n-impurity is also created in this way.
The layer of memristors connects layers of different levels and is the upper layer of the unit cell, the topology of which is shown in Fig.5.
A single layer is created on the chip, which is an analog of a planar two-layered logical matrix containing transistors in the lower layer, and memristors in the upper layer. The overlying layer is oriented crosswise to the bottom one, which is a prerequisite for the formation of commuting crossbars between the layers. Thus, the construction shown in Fig.6 is obtained.
To provide the necessary connections in the memory matrix, a layer of dielectric is added in the cell topology (Fig.7), in which pass-through buses providing access to the output of each inverter at the periphery of the matrix. To each such conductor of the overlying cell eight memristors of the cell are connected, which is located at the bottom, thus in one cell there are 8 Ч 8 = 64 memristors with series-connected Zener diodes. The number of memristors in the cell is determined by the area of the CMOS inverter. Further increase in the number of memristors implies an increase in the size of transistors.
The creation of 3D super-large logical matrix is possible by the technology of manufacturing multilayer chips containing CMOS structures in the upper layers .
The integration of planar two-layered logical matrices into a 3D structure provides a high integration of the elements due to the fact that the cell elements and the cells themselves are compactly stacked one above the other, while a significant reduction in the length of the connecting buses along the vertical and horizontal directions increases the performance and reduces power consumption.
To introduce an impurity into the semiconductor substrate, the rapid thermal alloying at 1 050 °C is used in the manufacture of transistors in the lower layer. CMOS transistors in the upper layers must be made at a temperature of 600 °C to avoid overheating of the entire structure and, first of all, melting of the conductors. For doping, a solid phase epitaxy is used.
To smooth the unevenness of the layers when they are spliced into the lower layer, an interlayer dielectric with a thickness of about 100 nm should be applied. After the obtaining of the interlayer dielectric, its top layer is leveled by chemical mechanical planarization (CMP) . The use of CMP allows to achieve a RMS roughness of the substrate of 0.2 nm, which is much better than the requirements for high-quality gluing.
The polished upper surface of the layer is spliced by low-temperature (200 °С) molecular bonding, developed for SOI substrates . The upper substrate is hydrophilically adhered at room temperature to the interlayer dielectric and then the controlled cleavage of the upper silicon layer is performed along the line of implanted hydrogen. After polishing the surface of the chip, a thin layer of monocrystalline silicon remains, which serves as the basis for the transistors of the next layer. In the resulting layer of monocrystalline silicon, the wells are etched using the TSV (Through-Silicon Via) technology, which are filled with metal for the upper conductors of the memristor crossbar. These conductors are the outputs of the inverters of the upper cells and combine the cathodes of the diodes of the underlying cell.
The topology of the logical and memory matrices based on CMOS memristor cells is presented, as well as vacuum nanotechnology for their manufacture, which combines classical silicon CMOS technology, as well as memristor crossbar technology, monolithic 3D integration and fabrication of vertically oriented Zener diodes. The topology of multilayer matrices is formed from identical layers consisting of layers created in successive technological operations so that each overlying layer is oriented perpendicularly to the underlying one. In this case, a three-dimensional structure is formed from elementary cells consisting of two transistors, a Zener diode and several memristors, where memristors perform switching electrical signals between layers.
The vacuum nanotechnology considered in this paper is compatible with up-to-date high-tech equipment for implementation of classical CMOS technology and does not require the use of additional equipment.
The presented topology allows to produce superlarge multi-layer memory and programmable logic matrices with a high degree of integration of elements that are necessary for creating a neuromorphic processor. ■