rus
Issue #9/2018
Korolev Andrey I., Jirkov Vladislav F., Bolshakov Kirill N., Benevolenskiy Dmitriy V.
Implementinf Polynomial Interpolation Block in Microcircuit for Position Sensor
Implementinf Polynomial Interpolation Block in Microcircuit for Position Sensor
This paper features peculiarities of implementation of special-purpose polynomial algorithm used for interpolation in microcircuit of precise position sensor. Block diagrams and calculation variants for main blocks have been considered. Main parameters and obtained results of implementation in X-Fab XH018 technological basis (180nm) have been provided.
Теги: digital signal processing high-precision approximation interpolation matlab microcircuit for position sensor polynomials verilog верилог высокоточная аппроксимация интерполяция матлаб микросхема для датчика положения полиномы цифровая обработка сигналов
INTRODUCTION
Interpolation is one of the typical subtasks which are being solved in modern microcircuits for position sensors. Such microcircuits are characterized by a narrow, restricted band of input signal and strict requirements for interpolation accuracy.
GOALS AND TASKS
The developed technique for interpolation using polynomials is designed to reduce occupied area and to provide operation of the interpolation block in several modes, but mainly — to provide high accuracy of signal retrieval [1, 2].
The Implementation of the interpolation block is provided in the form of Verilog-description and block synthesis using specialized CAD.
The requirements for the interpolation block were defined by the following specification:
normalized bandwidth of input signal from 0 to 1/8;
variable interpolation coefficient: 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048;
output data efficient number of bits (ENOB) = 9.16 bit.
The target basis of the developed position sensor microcircuit is XH018 microcircuits manufacturing technology with 180nm minimal element size developed by X-Fab [3]. The main criterions for the implementation efficiency are occupied area and maximum achievable clock frequency. Nevertheless, Verilog-description of the interpolation block has been developed as universal, applicable for synthesis by different technologies.
INTERPOLATION BLOCK DEVELOPMENT
At the stage of interpolation algorithms development, the following operations were performed:
1) the order of interpolation polynomial equal to 9 was selected, and matrix of constant (“M97b”) and scaling coefficients (B_coef”) were calculated;
2) coefficients bits number using integer model (20 and 16 bit respectively) as well as internal registers (33 bit) was estimated and specified.
For each in-coming reading the interpolation block performs the following actions:
1) organizing storage and data sampling at segment interval (10 readings);
2) calculating approximating polynomial coefficients;
3) calculating internal points of middle segment using Horner’s scheme.
This algorithm utilizes simple integer operations, such as: shift, summation, subtraction and multiplication. Due to the capacity of this basis to conduct in one clock period multiplication of numbers with definite digits, efficient serial-parallel processing was implemented.
The implemented polynomial interpolation algorithm enables one to perform abridged calculation of approximating coefficients. In this case low value coefficients of approximating polynomial computation are not performed, but instead are substituted by zeros. This reduces the amount of calculations at the cost of interpolation accuracy reduction. This mode of reduced computations was implemented in different degrees for 4 and 8 interpolation coefficients.
The reduced computations mode made it possible to maintain processability and versatility of the interpolation block implementation without increasing the area occupied by it.
To calculate approximating polynomial coefficients two multiplications of matrices are used. One of the operands in both cases is matrix of constants (Fig. 1).
Computation of intermediate coefficients “А” (Fig. 1а) consists of matrix row multiplication (values of data segment) by matrix of constant coefficients “M97b”. Values of data segment are input data (DI) stored in shift register RAM (“SR_RAM”). Matrix multiplications are carried out sequentially by operations of multiplications with accumulation (“MAC”).
This register memory is also used as element of matched delay for obtaining reference (central) value of retrieved segment (Y5).
Computation of approximating polynomial “B” (Fig. 1b) coefficients is performed by matrix multiplication of intermediate coefficients row “А” by scaling coefficients column. This operation also uses sequential computations by the first multiplier. To reduce requirements strictness for digits number of scaling coefficients, registers of multiplier and accumulator, multiplication results are shifted by algorithmically determined fixed values. This computational block of multiplication-shift-accumulation operations is designated on the diagram as “MSA” (Multiplication-Shift-Accumulation).
The main computational block consists of a set of control registers for intermediate fixation of polynomial coefficients (“B1”,. “B7”); a block of polynomial coefficients actualization and an output register-accumulator based on reference value (Fig. 2).
The block of polynomial coefficients actualization is the only one that uses parallel computing. As it uses only summation and shift operations, it occupies a small area of microcircuit (40 % of total area).
RESULTS
The research resulted in the development of architecture and hard-wired design of proposed algorithm, as well as Verilog-description of polynomial interpolation block, synthesised in the basis of custom integrated circuits. A number of performed tests revealed complete compliance between hardware description and integer MATLAB model for all the modes (interpolation coefficients). So we may resume that the following characteristics were attained for this block:
Attained functional characteristics generally comply with requirements for signal processing circuits used for position sensor with resolution of at least 16 bits and with high operation speed [4].
According to the synthesis program results, the area occupied by the implementation block makes 203681 micron2; this block successfully operates at clock frequency of 32МHz. In addition, the synthesis of this polynomial interpolation block was performed at digital library LPLIB using 180nm HCMOS8D technology developed by “Micron”, and according to the synthesis results the area occupied by this block makes 266997 micron2.
The authors consider the following provisions and results of the research as novel:
1) high performance characteristics of narrow band signal interpolation have been attained;
2) capability of efficient implementation of polynomial interpolation block has been confirmed.
CONCLUSION
The capability of obtaining such characteristics for the interpolation block was conditioned by consistent iterative work carried out simultaneously both for algorithm development and hardware implementation.
Polynomial interpolation was successfully implemented in the basis of custom microcircuits. At the same time, the following problems were solved: the appraisal of the very capability, the route of its implementation, estimation of attained characteristics and occupied area and, most important, the direct implementation of high-precision interpolation block.
This work was carried out with financial support provided by the Ministry of Education and Science of the Russian Federation within the project № 03.G25.31.0223.
REFERENCES
1. Zhirkov V. F., Sushkova L. T., Korolev A. I.,
Bol'shakov K. N., Obednin A. A., Prokof'-ev G. V. Polinomial'naya interpolyatsiya v tsifrovoi obrabotke signalov pri vysokikh trebovaniyakh k tochnosti. Zhurnal radioelektroniki [Electronic magazine]. 2017. № 4. http://jre.cplire.ru/jre/apr17/5/text.pdf. (In Russian).
2. Interpolyatsiya funktsii interpolyatsionnymi polinomami. // [Electronic resource]. URL: http://matlab.exponenta.ru/spline/index.php. (In Russian).
3. Prokof'ev G. V., Stakhin V. G., Obednin A. A. Sovremennye otechestvennye spetsializirovannye mikroskhemy dlya datchikov polozheniya. Izvestiya YuFU. Tekhnicheskie nauki № 3, 2015. P. 200–211. (In Russian).
4. Prokof'ev G. V., Bol'shakov K. N., Sta¬khin V. G. “Integral'nyi protsessor polozheniya dlya pretsizionnykh sistem upravleniya peremeshcheniem podvizhnykh uzlov i mekhanizmov”. Komponenty i tekhnologii, № 7, 2016. P. 81–85. (In Russian).
Interpolation is one of the typical subtasks which are being solved in modern microcircuits for position sensors. Such microcircuits are characterized by a narrow, restricted band of input signal and strict requirements for interpolation accuracy.
GOALS AND TASKS
The developed technique for interpolation using polynomials is designed to reduce occupied area and to provide operation of the interpolation block in several modes, but mainly — to provide high accuracy of signal retrieval [1, 2].
The Implementation of the interpolation block is provided in the form of Verilog-description and block synthesis using specialized CAD.
The requirements for the interpolation block were defined by the following specification:
normalized bandwidth of input signal from 0 to 1/8;
variable interpolation coefficient: 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048;
output data efficient number of bits (ENOB) = 9.16 bit.
The target basis of the developed position sensor microcircuit is XH018 microcircuits manufacturing technology with 180nm minimal element size developed by X-Fab [3]. The main criterions for the implementation efficiency are occupied area and maximum achievable clock frequency. Nevertheless, Verilog-description of the interpolation block has been developed as universal, applicable for synthesis by different technologies.
INTERPOLATION BLOCK DEVELOPMENT
At the stage of interpolation algorithms development, the following operations were performed:
1) the order of interpolation polynomial equal to 9 was selected, and matrix of constant (“M97b”) and scaling coefficients (B_coef”) were calculated;
2) coefficients bits number using integer model (20 and 16 bit respectively) as well as internal registers (33 bit) was estimated and specified.
For each in-coming reading the interpolation block performs the following actions:
1) organizing storage and data sampling at segment interval (10 readings);
2) calculating approximating polynomial coefficients;
3) calculating internal points of middle segment using Horner’s scheme.
This algorithm utilizes simple integer operations, such as: shift, summation, subtraction and multiplication. Due to the capacity of this basis to conduct in one clock period multiplication of numbers with definite digits, efficient serial-parallel processing was implemented.
The implemented polynomial interpolation algorithm enables one to perform abridged calculation of approximating coefficients. In this case low value coefficients of approximating polynomial computation are not performed, but instead are substituted by zeros. This reduces the amount of calculations at the cost of interpolation accuracy reduction. This mode of reduced computations was implemented in different degrees for 4 and 8 interpolation coefficients.
The reduced computations mode made it possible to maintain processability and versatility of the interpolation block implementation without increasing the area occupied by it.
To calculate approximating polynomial coefficients two multiplications of matrices are used. One of the operands in both cases is matrix of constants (Fig. 1).
Computation of intermediate coefficients “А” (Fig. 1а) consists of matrix row multiplication (values of data segment) by matrix of constant coefficients “M97b”. Values of data segment are input data (DI) stored in shift register RAM (“SR_RAM”). Matrix multiplications are carried out sequentially by operations of multiplications with accumulation (“MAC”).
This register memory is also used as element of matched delay for obtaining reference (central) value of retrieved segment (Y5).
Computation of approximating polynomial “B” (Fig. 1b) coefficients is performed by matrix multiplication of intermediate coefficients row “А” by scaling coefficients column. This operation also uses sequential computations by the first multiplier. To reduce requirements strictness for digits number of scaling coefficients, registers of multiplier and accumulator, multiplication results are shifted by algorithmically determined fixed values. This computational block of multiplication-shift-accumulation operations is designated on the diagram as “MSA” (Multiplication-Shift-Accumulation).
The main computational block consists of a set of control registers for intermediate fixation of polynomial coefficients (“B1”,. “B7”); a block of polynomial coefficients actualization and an output register-accumulator based on reference value (Fig. 2).
The block of polynomial coefficients actualization is the only one that uses parallel computing. As it uses only summation and shift operations, it occupies a small area of microcircuit (40 % of total area).
RESULTS
The research resulted in the development of architecture and hard-wired design of proposed algorithm, as well as Verilog-description of polynomial interpolation block, synthesised in the basis of custom integrated circuits. A number of performed tests revealed complete compliance between hardware description and integer MATLAB model for all the modes (interpolation coefficients). So we may resume that the following characteristics were attained for this block:
Attained functional characteristics generally comply with requirements for signal processing circuits used for position sensor with resolution of at least 16 bits and with high operation speed [4].
According to the synthesis program results, the area occupied by the implementation block makes 203681 micron2; this block successfully operates at clock frequency of 32МHz. In addition, the synthesis of this polynomial interpolation block was performed at digital library LPLIB using 180nm HCMOS8D technology developed by “Micron”, and according to the synthesis results the area occupied by this block makes 266997 micron2.
The authors consider the following provisions and results of the research as novel:
1) high performance characteristics of narrow band signal interpolation have been attained;
2) capability of efficient implementation of polynomial interpolation block has been confirmed.
CONCLUSION
The capability of obtaining such characteristics for the interpolation block was conditioned by consistent iterative work carried out simultaneously both for algorithm development and hardware implementation.
Polynomial interpolation was successfully implemented in the basis of custom microcircuits. At the same time, the following problems were solved: the appraisal of the very capability, the route of its implementation, estimation of attained characteristics and occupied area and, most important, the direct implementation of high-precision interpolation block.
This work was carried out with financial support provided by the Ministry of Education and Science of the Russian Federation within the project № 03.G25.31.0223.
REFERENCES
1. Zhirkov V. F., Sushkova L. T., Korolev A. I.,
Bol'shakov K. N., Obednin A. A., Prokof'-ev G. V. Polinomial'naya interpolyatsiya v tsifrovoi obrabotke signalov pri vysokikh trebovaniyakh k tochnosti. Zhurnal radioelektroniki [Electronic magazine]. 2017. № 4. http://jre.cplire.ru/jre/apr17/5/text.pdf. (In Russian).
2. Interpolyatsiya funktsii interpolyatsionnymi polinomami. // [Electronic resource]. URL: http://matlab.exponenta.ru/spline/index.php. (In Russian).
3. Prokof'ev G. V., Stakhin V. G., Obednin A. A. Sovremennye otechestvennye spetsializirovannye mikroskhemy dlya datchikov polozheniya. Izvestiya YuFU. Tekhnicheskie nauki № 3, 2015. P. 200–211. (In Russian).
4. Prokof'ev G. V., Bol'shakov K. N., Sta¬khin V. G. “Integral'nyi protsessor polozheniya dlya pretsizionnykh sistem upravleniya peremeshcheniem podvizhnykh uzlov i mekhanizmov”. Komponenty i tekhnologii, № 7, 2016. P. 81–85. (In Russian).
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