rus
Issue #9/2018
Volkov Svyatoslav I., Bobkov Sergey G., Krasnyuk Andrey A.
Test Structures for Microprocessor Systems for High-temperature Microelectronics
Test Structures for Microprocessor Systems for High-temperature Microelectronics
SOI CMOS technology has an absolute advantage over wide band gap semiconductors, memory cells like MRAM and FRAM especially for the development of super-large-scale integrated circuits of memory, microprocessors and systems on a chip for maximum operating temperatures up to 250–300 °C. In the work, I–V characteristic of transistors, switching and time characteristics of trigger memories and ring generators were investigated. A series of experiments was also carried out to study the influence of the temperature on the transistors and design techniques. Based on the data we have investigated, it is shown that a temperature change up to 250 °C causes not only an increase in leakage currents by 3–4 orders of magnitude, but also the impact ionization and the kink effect. Experimental studies of ring generators have shown that when the temperature varies from 25 ° C to 200 °C, the generation frequency decreases by a factor of 1.5, the static current of consumption increases by three orders of magnitude (up to 0,5 μA), and the dynamic current of consumption increases by 40 %.The research of test structures of trigger memory elements, showed unconditional shift to the left with decreasing critical points for families of switching characteristics. In general, the noise immunity of memory cells in the investigated temperature range varies insignificantly — up to 10 %, which makes it possible to conclude that it is possible to build static memory blocks in high-temperature microprocessors without fundamental changes in circuitry. So on, the conclusion is made on the principle possibility of creating microprocessor systems based on the developed circuit elements for operating temperatures up to 300 °C.
Теги: high-temperature microelectronics ip cores layout vlsi microprocessors soi cmos высокотемпературная электроника микропроцессоры топология сбис
INTRODUCTION
Today high-temperature electronics (HTE) is one of the most rapidly developing areas of electronics, which is due to the needs of industrial electronics, geological exploration, automobile and aircraft construction, rocket and space technology, and the tasks of physical experiment. The term “HTE” refers to electronics operating at temperatures above 150 °C. The creation of high-temperature microcircuits requires the solution of the following main tasks. The first of them consists in choosing a technological basis that provides leakage currents acceptable for operation, associated with generation-recombination processes in p-n junctions. The second is to find such constructive and technological solutions that will ensure a sufficient level of reliability of manufactured products, since the characteristic degradation processes leading to failures, with increasing temperature, are significantly activated. The third task is to find such architectural and circuit solutions that will minimize the effect of significant changes in the dynamic parameters of the basic elements on the operation of the chip. And finally, the fourth challenge is in defining and shaping design methodology, VLSI high-temperature resistant, enabling the use in electronic components for industrial and space systems, which requires the formation of specialized design rules, significantly different from both common rules for the VLSI, ASIC and system-on-chip (SoC). The main difference is due to the need of considering additional destructive factors, such as single faults (SEE), and dose effects (TID), the temperature not only at the stage of the formation of working libraries and models, but also on the stages of layout design, routing, verification, RC extraction, and testing. Formation and investigation of the relevant test elements creates the necessary prerequisites for the development of a basic high-temperature technology [1].
THE CHOICE OF UNDERLYING TECHNOLOGY
As a result of a comparative analysis of the physical characteristics of transistor structures at extremely high temperatures, the main physical effects critical for high temperature technologies were identified:
change of the main characteristics of VLSI elements due to the variations of parameters such as: density and concentration of carriers increase with extreme temperatures; leakage currents of p-n junctions are doubled for every 10 °C; mobility of carriers decreases with increasing temperature; resistances and threshold voltages — usually a linear increase with temperature; resistance and threshold voltage is generally linear increase with temperature; factor of parasitic electrodiffusion and migration of carriers [2];
problems of trace and layout of the circuits;
significant decrease in the operability and endurance of VLSI during extreme operating conditions.
Experimental studies have shown that in practice, for many types of ICs, there is no correlation between the failure rate and the p-n-junction temperature, that is, there is no exponential dependence of the number of failures on temperature. In a properly designed microelectronics product, the temperature effects can be compensated for, so that in temperate temperature ranges this factor can be eliminated.
Technological solutions
SOI technology provides 100 times smaller area of formation of leakage current to the drain regions of transistors compared to bulk MOS technologies [3]. Technology MRAM and FRAM are also based on electronic CMOS frame and respectively bounded by the high temperature circuit parameters of the frame. From the point of view of radiation resistance the memory elements on the basis of MRAM and FRAM have an advantage over CMOS memory devices (memory), but with the temperature factor the resistance and durability of the respective memory are significantly lower than in SOI CMOS technologies [4].
According to the results of the analysis of high temperature and extreme capabilities of the existing microelectronic technology it is possible to draw the following basic conclusion:
SOI CMOS technology has an absolute advantage over volumetric TIR and technologies based on wide bandgap semiconductors, memory elements of the type MRAM and FRAM in the development of very large scale integrated memory circuits, microprocessors and systems-on-chip in the housing for maximum operating temperature 250–300 °C. For temperatures above 300 °C, the priority of the electronic component base are the structures based on wide bandgap semiconductors and on new physical principles [5].
Thus, the fundamental choice of the SOI technology as a technological basis for creating high temperature circuits for maximum operating temperature up to 250–300 °C is crucial for most practical applications [6]. One of the most important challenges for this research area is to identify the key criteria and estimates for the formation and extraction of basic SPICE parameters of VLSI elements, in particular the drain-gate characteristics of the transistors for temperatures from –60 °C to 300 °C; the temperature dependence for the switching characteristics of the trigger memory cell; according to the time of the establishment of the logical zero and one temperature, etc.
Using SOI CMOS process allows us to design chips with a supply voltage of 3.3V or 5.0V with design rules of 0.5µm based on partially depleted SOI CMOS (PDSOI) transistors with STI-isolation. Hidden oxide has a thickness of 143nm and is manufactured by a SIMOX-like technology [7]. The advantages of this technology include:
increased resistance of the IC to influence of heavy charged particles, compared with the bulk CMOS technology (with contact to the “body”);
the possibility of switching the “body” of both the p- and n-channel SOI transistors: the connection with the source or supply (ground). Within the chosen technological direction there is a possibility of complete electrical isolation of each circuit element, which drastically reduces the leakage current compared to the technology on bulk silicon.
Components of the test structures
For carrying out high-temperature studies, we used:
N-channel transistors (same as in memory cells) without protection circuits, with parallel inclusion of n-channel a-type transistors — the channel body and source are connected by a jumper. The structure has 3 outputs — drain, source and gate.
N-channel (same as in memory cells) with protection circuits, (protection — p-channel transistor in diode switching, gate connected to source), parallel connection of n-channel a-type transistors.
P-channel transistors (same as in memory cells) without protection circuits, parallel to up to 20 p-channel a-type transistors.
P- channel (same as in memory cells) with protection circuits, 3 pins (protection — p-channel transistor in diode switch, gate connected to source). An example of the construction of transistors is shown in Fig. 1. Fig. 2 shows an example of the layout of transistors with protection circuits.
The corresponding design of memory cells for test structures is shown in Fig. 3. Fig. 4 shows the circuit of a test ring generator consisting of 301 inverters with a-type transistors [8, 9]. This is due to the fact that a-type transistors have the body rigidly connected to the drain. In this case, the effects inherent in transistors with a “floating” body are completely suppressed, although the problem of the asymmetry of the drain and the source arises. The asymmetry leads to uncertainty in the effective width of the transistor. However, the comparison of the experimental I–V characteristics of a-type transistors and transistors with a “floating” body shows that, with the same drain width, the effective channel width of a-type transistors is smaller. In this regard, it is necessary to correctly calculate the width of a-type transistors and integrate this calculation into design rules. A feature of SOI test structures is the arrangement of elements on so-called “islands” of silicon, separated by insulation. This raises the parasitic lateral transistors and the bottom transistor, whose impact must be considered in the simulation [10].
The lateral parasitic transistor has a variable thickness of the “gate” oxide, whose role is played by islands of insulation. The influence of the lateral transistor is detected by structures consisting of parallel-connected transistors of the same total width as one and the same transistor. To assess the influence of the potential of the body, H-type structures are used. The appearance of the lower transistor is possible due to the presence of a hidden oxide (box), the role of the gate is performed by the substrate. The effect of this structure is estimated with the aid of a ring transistor in which there are no side parasitic transistors, feeding a zero potential to the gate [11]. Below are some results of experimental and theoretical studies of the behavior of elements and structures formed in the CMOS SOI 0.5μm process.
RESULTS OF EXPERIMENTAL STUDIES OF TEST STRUCTURES
Due to technical limitations, experimental studies were carried out in the temperature range 25–200 °C, theoretical estimates (based on process simulation) in the range 25–275 °C. Fig. 5 shows the experimental dependences of the leakage current — a) and the operating current — b) for CMOS SOI transistors with L = 0.5μm, W = 3μm on temperature.
The temperature change at 250 °C causes not only a change in the leakage currents by 3–4 orders of magnitude, but also the formation of shock ionization regions and the kink effect, as shown on Fig. 5b. Fig. 6 and Fig. 7 show the results of measurements of 5 test structures for temperatures of 25 °C and 200 °C. Fig. 6a shows the decrease in the threshold voltage for an N-channel A-type transistor. Fig. 6b shows the corresponding decrease in the steepness of this type of transistors. The study of ring transistor (o-type) that does not have lateral parasitic transistors shown in Fig. 7, shows the almost complete absence of the contribution of lateral parasitic transistors in the deterioration of the main characteristics of SOI transistors for extreme temperatures. Fig. 7a shows a decrease in threshold voltage for N-channel transistor of o-type. Fig. 7b shows the corresponding decrease in the transconductance of this type of transistors.
Fig. 8–10 show the results of measurements of 4 samples of ring generators (CG) consisting of 301 inverters with a-type transistors. As can be seen, with a temperature change from 25 °C to 200 °C, the generation frequency decreases by a factor of 1.5, the static current of consumption increases by three orders of magnitude (up to 0.5μA), and the dynamic current of consumption increases by 40 %.
The formation of change of current of consumption with temperature is given in Fig. 9.
Fig. 11 shows the shift of the switching characteristic of the 6-transistor trigger (Fig. 3) as a function of temperature. With a supply voltage of 5V corresponding changes in the noise immunity of the trigger memory elements will not exceed 10 %, which allows one to make a conclusion about the possibility of building embedded static memories in high temperature microprocessors without fundamental changes in design and construction of functional memory elements [12].
CONCLUSIONS
The results obtained make it possible to draw the following conclusions:
SOI CMOS technology has an absolute advantage over wide band gap semiconductors, memory cells like MRAM and FRAM by development of super-large-scale integrated circuits of memory, microprocessors and systems on a chip for maximum operating temperatures up to 250–300 °C. However, for SOI CMOS transistor structures maximum working temperature is 250 °C with the possibility of short-term overheating to 300 °C, which is a critical parameter. The obtained results confirm the nature of the change in temperature dependences for the SOI CMOS structures.
A series of experiments was also carried out to study the influence of the temperature on the transistors and design techniques. Based on the data we have investigated, it is shown that a temperature change up to 250 °C causes not only an increase in leakage currents by 3–4 orders of magnitude, but also the impact ionization and the kink effect. Experimental studies of ring generators have shown that when the temperature varies from 25 °C to 200 °C, the generation frequency decreases by a factor of 1.5, the static current of consumption increases by three orders of magnitude (up to 0.5μA), and the dynamic current of consumption increases by 40 %.The research of test structures of trigger memory elements showed unconditional shift to the left with decreasing critical points for families of switching characteristics. In general, the noise immunity of memory cells in the investigated temperature range varies insignificantly — up to 10 %, which makes it possible to conclude that it is possible to build static memory blocks in high-temperature microprocessors without fundamental changes in circuitry. So, the conclusion is made on the principle possibility of creating microprocessor systems based on the developed circuit elements for operating temperatures up to 300 °C.
General recommendations for the HTE systems correspond in many respects to the well-known practices for developing Low Power (LP) and Ultra Low Power (ULP) systems, allowing you to use the same proven design rules [13].
This work is supported by Russian Foundation for Basic Research, grant № 14-29-09207.
REFERENCES
1.
Johnson R. W., Evans J. L., P. Jacobsen, J. R. (Rick) Thompson, and Mark Christopher. “The Changing Automotive Environment: High-Temperature Electronics”, IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, VOL. 27, NO. 3, JULY 2004.
2. Nowosielski R., Hartig J., Payá-Vayá G., Blume H. “Exploring Different Approximate Adder Architecture Implementations in a 250 °C SOI Technology”. 1st Workshop On Approximate Computing (WAPCO 2015), in Conjunction with HiPEAC 2015, Amsterdam, Netherlands, 2015.
3. Thomas Romanko, Applications Engineer, Honeywell Aerospace. Extreme Design: Developing Integrated Circuits for –55 °C to +250 °C. 10 November 2008.
4. Lowther R., Gifford D., Morrus W., Jensen J., Peterson S., Atkinson K. “Enabling Bulk Silicon CMOS Technology for Integration, Reliability, and Extended Lifetime at High Temperature”, International Conference at Exhibition on High Temperature Electronics Network (HiTEN), July 6–8, 2015, Cambridge, UK.
5. Ohme B. W., Johnson B. J., and Mark R. Larson, “SOI CMOS for Extreme Temperature Applications”, Honeywell Aerospace, Defense & Space Honeywell International Plymouth, Minnesota, SA, 55441.
6. Ohme B. W., Larson M. R., Riekels J., Schlesinger S., Vignarajah K., and Ericson M. N. “Progress Update on Honeywell’s DeepTrek High Temperature Electronics Project”, IMAPS Int’l. Conference on High Temperature Electronics (HiTEC), May 2006.
7. Bobkov S. G., Galper A. M., Bonvicini V., Topchiev N. P., (…), Zirakashvili V. N., Zverev V. G. The Unification of Space Qualified Integrated Circuits by Example of International Space Project GAMMA-400 // Physics Procedia, 2015, № 74, pp. 224–231.
8. Huque M. A. et al. “An SOI-based High-Voltage, High-Temperature Gate-Driver for SiC FET”. IEEE Xplore (2007).
9. Stenin V. Ya., Stepanov P. V. Basic Memory Elements Using DICE Cells for Fault-Tolerant 28nm CMOS RAM // Russian Microelectronics. 2015. Vol. 44. № 6, pp. 368–379.
10. Dreiner S., Kappert H., Dittrich D., Grella K., Kelberer A., Klusmann M., Kordas N., Kosfeld A., Schmidt A., Paschen U., Kokozinski R. “HIGH TEMPERATURE 0.35 MICRON SOI CMOS PROCESS (250 °C AND BEYOND)”, Fraunhofer Institute for Microelectronic Circuits and Systems IMS, Germany [Online]. Available: http://www.ims.fraunhofer.de.
11. Fraunhofer Institute. (2014, Nov.) High Temperature SOI Technology H10. [Online]. Available: http://www.ims.fraunhofer.de.
12. Krasnyuk A. A., Orlov O. M., Imametdinov E. F., and Mar’ina E. V. Analysis of Characteristics for Periodically Doped Channel Field-Effect Transistors Under Extreme Thermal Conditions // Russian Microelectronics. 2015. Vol. 44. № 4, pp. 231–235.
13. Marshall, Andrew and Sreedhar Natarajan. “High-Voltage and Power Applications”. SOI Design: Analog, Memory and Digital Techniques. Kluwer Academic Publishers, 2002. 1, 51–57,
312.
Today high-temperature electronics (HTE) is one of the most rapidly developing areas of electronics, which is due to the needs of industrial electronics, geological exploration, automobile and aircraft construction, rocket and space technology, and the tasks of physical experiment. The term “HTE” refers to electronics operating at temperatures above 150 °C. The creation of high-temperature microcircuits requires the solution of the following main tasks. The first of them consists in choosing a technological basis that provides leakage currents acceptable for operation, associated with generation-recombination processes in p-n junctions. The second is to find such constructive and technological solutions that will ensure a sufficient level of reliability of manufactured products, since the characteristic degradation processes leading to failures, with increasing temperature, are significantly activated. The third task is to find such architectural and circuit solutions that will minimize the effect of significant changes in the dynamic parameters of the basic elements on the operation of the chip. And finally, the fourth challenge is in defining and shaping design methodology, VLSI high-temperature resistant, enabling the use in electronic components for industrial and space systems, which requires the formation of specialized design rules, significantly different from both common rules for the VLSI, ASIC and system-on-chip (SoC). The main difference is due to the need of considering additional destructive factors, such as single faults (SEE), and dose effects (TID), the temperature not only at the stage of the formation of working libraries and models, but also on the stages of layout design, routing, verification, RC extraction, and testing. Formation and investigation of the relevant test elements creates the necessary prerequisites for the development of a basic high-temperature technology [1].
THE CHOICE OF UNDERLYING TECHNOLOGY
As a result of a comparative analysis of the physical characteristics of transistor structures at extremely high temperatures, the main physical effects critical for high temperature technologies were identified:
change of the main characteristics of VLSI elements due to the variations of parameters such as: density and concentration of carriers increase with extreme temperatures; leakage currents of p-n junctions are doubled for every 10 °C; mobility of carriers decreases with increasing temperature; resistances and threshold voltages — usually a linear increase with temperature; resistance and threshold voltage is generally linear increase with temperature; factor of parasitic electrodiffusion and migration of carriers [2];
problems of trace and layout of the circuits;
significant decrease in the operability and endurance of VLSI during extreme operating conditions.
Experimental studies have shown that in practice, for many types of ICs, there is no correlation between the failure rate and the p-n-junction temperature, that is, there is no exponential dependence of the number of failures on temperature. In a properly designed microelectronics product, the temperature effects can be compensated for, so that in temperate temperature ranges this factor can be eliminated.
Technological solutions
SOI technology provides 100 times smaller area of formation of leakage current to the drain regions of transistors compared to bulk MOS technologies [3]. Technology MRAM and FRAM are also based on electronic CMOS frame and respectively bounded by the high temperature circuit parameters of the frame. From the point of view of radiation resistance the memory elements on the basis of MRAM and FRAM have an advantage over CMOS memory devices (memory), but with the temperature factor the resistance and durability of the respective memory are significantly lower than in SOI CMOS technologies [4].
According to the results of the analysis of high temperature and extreme capabilities of the existing microelectronic technology it is possible to draw the following basic conclusion:
SOI CMOS technology has an absolute advantage over volumetric TIR and technologies based on wide bandgap semiconductors, memory elements of the type MRAM and FRAM in the development of very large scale integrated memory circuits, microprocessors and systems-on-chip in the housing for maximum operating temperature 250–300 °C. For temperatures above 300 °C, the priority of the electronic component base are the structures based on wide bandgap semiconductors and on new physical principles [5].
Thus, the fundamental choice of the SOI technology as a technological basis for creating high temperature circuits for maximum operating temperature up to 250–300 °C is crucial for most practical applications [6]. One of the most important challenges for this research area is to identify the key criteria and estimates for the formation and extraction of basic SPICE parameters of VLSI elements, in particular the drain-gate characteristics of the transistors for temperatures from –60 °C to 300 °C; the temperature dependence for the switching characteristics of the trigger memory cell; according to the time of the establishment of the logical zero and one temperature, etc.
Using SOI CMOS process allows us to design chips with a supply voltage of 3.3V or 5.0V with design rules of 0.5µm based on partially depleted SOI CMOS (PDSOI) transistors with STI-isolation. Hidden oxide has a thickness of 143nm and is manufactured by a SIMOX-like technology [7]. The advantages of this technology include:
increased resistance of the IC to influence of heavy charged particles, compared with the bulk CMOS technology (with contact to the “body”);
the possibility of switching the “body” of both the p- and n-channel SOI transistors: the connection with the source or supply (ground). Within the chosen technological direction there is a possibility of complete electrical isolation of each circuit element, which drastically reduces the leakage current compared to the technology on bulk silicon.
Components of the test structures
For carrying out high-temperature studies, we used:
N-channel transistors (same as in memory cells) without protection circuits, with parallel inclusion of n-channel a-type transistors — the channel body and source are connected by a jumper. The structure has 3 outputs — drain, source and gate.
N-channel (same as in memory cells) with protection circuits, (protection — p-channel transistor in diode switching, gate connected to source), parallel connection of n-channel a-type transistors.
P-channel transistors (same as in memory cells) without protection circuits, parallel to up to 20 p-channel a-type transistors.
P- channel (same as in memory cells) with protection circuits, 3 pins (protection — p-channel transistor in diode switch, gate connected to source). An example of the construction of transistors is shown in Fig. 1. Fig. 2 shows an example of the layout of transistors with protection circuits.
The corresponding design of memory cells for test structures is shown in Fig. 3. Fig. 4 shows the circuit of a test ring generator consisting of 301 inverters with a-type transistors [8, 9]. This is due to the fact that a-type transistors have the body rigidly connected to the drain. In this case, the effects inherent in transistors with a “floating” body are completely suppressed, although the problem of the asymmetry of the drain and the source arises. The asymmetry leads to uncertainty in the effective width of the transistor. However, the comparison of the experimental I–V characteristics of a-type transistors and transistors with a “floating” body shows that, with the same drain width, the effective channel width of a-type transistors is smaller. In this regard, it is necessary to correctly calculate the width of a-type transistors and integrate this calculation into design rules. A feature of SOI test structures is the arrangement of elements on so-called “islands” of silicon, separated by insulation. This raises the parasitic lateral transistors and the bottom transistor, whose impact must be considered in the simulation [10].
The lateral parasitic transistor has a variable thickness of the “gate” oxide, whose role is played by islands of insulation. The influence of the lateral transistor is detected by structures consisting of parallel-connected transistors of the same total width as one and the same transistor. To assess the influence of the potential of the body, H-type structures are used. The appearance of the lower transistor is possible due to the presence of a hidden oxide (box), the role of the gate is performed by the substrate. The effect of this structure is estimated with the aid of a ring transistor in which there are no side parasitic transistors, feeding a zero potential to the gate [11]. Below are some results of experimental and theoretical studies of the behavior of elements and structures formed in the CMOS SOI 0.5μm process.
RESULTS OF EXPERIMENTAL STUDIES OF TEST STRUCTURES
Due to technical limitations, experimental studies were carried out in the temperature range 25–200 °C, theoretical estimates (based on process simulation) in the range 25–275 °C. Fig. 5 shows the experimental dependences of the leakage current — a) and the operating current — b) for CMOS SOI transistors with L = 0.5μm, W = 3μm on temperature.
The temperature change at 250 °C causes not only a change in the leakage currents by 3–4 orders of magnitude, but also the formation of shock ionization regions and the kink effect, as shown on Fig. 5b. Fig. 6 and Fig. 7 show the results of measurements of 5 test structures for temperatures of 25 °C and 200 °C. Fig. 6a shows the decrease in the threshold voltage for an N-channel A-type transistor. Fig. 6b shows the corresponding decrease in the steepness of this type of transistors. The study of ring transistor (o-type) that does not have lateral parasitic transistors shown in Fig. 7, shows the almost complete absence of the contribution of lateral parasitic transistors in the deterioration of the main characteristics of SOI transistors for extreme temperatures. Fig. 7a shows a decrease in threshold voltage for N-channel transistor of o-type. Fig. 7b shows the corresponding decrease in the transconductance of this type of transistors.
Fig. 8–10 show the results of measurements of 4 samples of ring generators (CG) consisting of 301 inverters with a-type transistors. As can be seen, with a temperature change from 25 °C to 200 °C, the generation frequency decreases by a factor of 1.5, the static current of consumption increases by three orders of magnitude (up to 0.5μA), and the dynamic current of consumption increases by 40 %.
The formation of change of current of consumption with temperature is given in Fig. 9.
Fig. 11 shows the shift of the switching characteristic of the 6-transistor trigger (Fig. 3) as a function of temperature. With a supply voltage of 5V corresponding changes in the noise immunity of the trigger memory elements will not exceed 10 %, which allows one to make a conclusion about the possibility of building embedded static memories in high temperature microprocessors without fundamental changes in design and construction of functional memory elements [12].
CONCLUSIONS
The results obtained make it possible to draw the following conclusions:
SOI CMOS technology has an absolute advantage over wide band gap semiconductors, memory cells like MRAM and FRAM by development of super-large-scale integrated circuits of memory, microprocessors and systems on a chip for maximum operating temperatures up to 250–300 °C. However, for SOI CMOS transistor structures maximum working temperature is 250 °C with the possibility of short-term overheating to 300 °C, which is a critical parameter. The obtained results confirm the nature of the change in temperature dependences for the SOI CMOS structures.
A series of experiments was also carried out to study the influence of the temperature on the transistors and design techniques. Based on the data we have investigated, it is shown that a temperature change up to 250 °C causes not only an increase in leakage currents by 3–4 orders of magnitude, but also the impact ionization and the kink effect. Experimental studies of ring generators have shown that when the temperature varies from 25 °C to 200 °C, the generation frequency decreases by a factor of 1.5, the static current of consumption increases by three orders of magnitude (up to 0.5μA), and the dynamic current of consumption increases by 40 %.The research of test structures of trigger memory elements showed unconditional shift to the left with decreasing critical points for families of switching characteristics. In general, the noise immunity of memory cells in the investigated temperature range varies insignificantly — up to 10 %, which makes it possible to conclude that it is possible to build static memory blocks in high-temperature microprocessors without fundamental changes in circuitry. So, the conclusion is made on the principle possibility of creating microprocessor systems based on the developed circuit elements for operating temperatures up to 300 °C.
General recommendations for the HTE systems correspond in many respects to the well-known practices for developing Low Power (LP) and Ultra Low Power (ULP) systems, allowing you to use the same proven design rules [13].
This work is supported by Russian Foundation for Basic Research, grant № 14-29-09207.
REFERENCES
1.
Johnson R. W., Evans J. L., P. Jacobsen, J. R. (Rick) Thompson, and Mark Christopher. “The Changing Automotive Environment: High-Temperature Electronics”, IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, VOL. 27, NO. 3, JULY 2004.
2. Nowosielski R., Hartig J., Payá-Vayá G., Blume H. “Exploring Different Approximate Adder Architecture Implementations in a 250 °C SOI Technology”. 1st Workshop On Approximate Computing (WAPCO 2015), in Conjunction with HiPEAC 2015, Amsterdam, Netherlands, 2015.
3. Thomas Romanko, Applications Engineer, Honeywell Aerospace. Extreme Design: Developing Integrated Circuits for –55 °C to +250 °C. 10 November 2008.
4. Lowther R., Gifford D., Morrus W., Jensen J., Peterson S., Atkinson K. “Enabling Bulk Silicon CMOS Technology for Integration, Reliability, and Extended Lifetime at High Temperature”, International Conference at Exhibition on High Temperature Electronics Network (HiTEN), July 6–8, 2015, Cambridge, UK.
5. Ohme B. W., Johnson B. J., and Mark R. Larson, “SOI CMOS for Extreme Temperature Applications”, Honeywell Aerospace, Defense & Space Honeywell International Plymouth, Minnesota, SA, 55441.
6. Ohme B. W., Larson M. R., Riekels J., Schlesinger S., Vignarajah K., and Ericson M. N. “Progress Update on Honeywell’s DeepTrek High Temperature Electronics Project”, IMAPS Int’l. Conference on High Temperature Electronics (HiTEC), May 2006.
7. Bobkov S. G., Galper A. M., Bonvicini V., Topchiev N. P., (…), Zirakashvili V. N., Zverev V. G. The Unification of Space Qualified Integrated Circuits by Example of International Space Project GAMMA-400 // Physics Procedia, 2015, № 74, pp. 224–231.
8. Huque M. A. et al. “An SOI-based High-Voltage, High-Temperature Gate-Driver for SiC FET”. IEEE Xplore (2007).
9. Stenin V. Ya., Stepanov P. V. Basic Memory Elements Using DICE Cells for Fault-Tolerant 28nm CMOS RAM // Russian Microelectronics. 2015. Vol. 44. № 6, pp. 368–379.
10. Dreiner S., Kappert H., Dittrich D., Grella K., Kelberer A., Klusmann M., Kordas N., Kosfeld A., Schmidt A., Paschen U., Kokozinski R. “HIGH TEMPERATURE 0.35 MICRON SOI CMOS PROCESS (250 °C AND BEYOND)”, Fraunhofer Institute for Microelectronic Circuits and Systems IMS, Germany [Online]. Available: http://www.ims.fraunhofer.de.
11. Fraunhofer Institute. (2014, Nov.) High Temperature SOI Technology H10. [Online]. Available: http://www.ims.fraunhofer.de.
12. Krasnyuk A. A., Orlov O. M., Imametdinov E. F., and Mar’ina E. V. Analysis of Characteristics for Periodically Doped Channel Field-Effect Transistors Under Extreme Thermal Conditions // Russian Microelectronics. 2015. Vol. 44. № 4, pp. 231–235.
13. Marshall, Andrew and Sreedhar Natarajan. “High-Voltage and Power Applications”. SOI Design: Analog, Memory and Digital Techniques. Kluwer Academic Publishers, 2002. 1, 51–57,
312.
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