Multigate Mosfet Model With a Quantum Dot in the Channel
The problems of the development of the submicron transistor constructions, which could allow building up a new types of CMOS and SOI CMOS µP chips for high temperature and radiation factors seem to be very important. One of potential ways of the solving this problem is developing and applying new types of MOSFET transistors such as multigate and split gate transistor structures with periodically doped channel in hard circuit. Nanoscale MOS transistor structures with split gate (SGMOS) provide the possibility of forming one-dimensional and two-dimensional elements in the hidden layer of a two-dimensional electron gas. It is believed that the use of the split electrodes is most effective in modulation-doped structures and less effective in delta-doped samples . In [2–5], the PDCFET (periodically doped channel) models, in which a modulation-doped channel is used, were considered. The problem of investigating such structures as split-gate MOS seems to be topical, since it makes it possible to consider the possibility of creating on their basis a number of sensors and transducers, in particular for devices based on surface plasmon resonance (SPR) .
The main objective of the study is to develop new transistor structures using instrumental and technological models for using in sensors and transducers design for high temperature electronics, as well as the study of the characteristics of obtained structures for devices based on SPR methods.
The research subject of this article is the multigate CMOS transistor structure with periodically doped channel with the capacities of basic structure of 0.5µm CMOS SOI HT (high temperature) technologies [7, 8]. In the frame of this work there have been formed models of n- and p-channel MOS transistor structures, which have been simulated by the device-technological analysis. The peculiarity of such structure consists in the specific modulation doping of the transistor channel (Fig. 1). Use of multigate transistors based on MOS structures with modulation of channel conductivity (PDCFET) for our project can have a number of significant advantages over the traditional approach. The analysis of characteristics of this model in the presence of high temperature is also the concern of this project.
During simulation there has been observed a special processing route, where the main idea is contained in the additory ion-implant doping of arsenic for the n-channel transistor and of boron for p-channel transistor. As a result, the channel of the transistor in question obtains the periodicity of doping. Also in the process of the formation of the research structures there have been contemplated light-doped LDD-regions, which lengthen drain and source regions towards the channel [9, 10]. For isolation the gate of the transistor is surrounded by the delimitative layer in the form of a thick silicon oxidation film . For furthermost consideration in the article there will be analyzed only n-channel MOS transistor and its characteristics. The results of physical simulation of the doping distribution at horizontal section are shown in Fig. 2.
According to the abovementioned plots it could be said that:
effective channel length is 0.25µm;
during the formation of n-diffused area the maximum of doping concentration is at 3.16 · 1020cm−3;
during the formation of the region under the gate, which is formed by the additory boron implant doping, the maximum of doping concentration appears at interface of silicon — silicon oxide.
The dependences of the I–V characteristics on the level of doping of the island in the channel of the transistor and its length were estimated, which are shown in Fig. 3 and Fig. 4, respectively. The results show the expected increase in the transconductance and a decrease in the threshold voltage with increasing doping level of the island, which is explained by the model approximation to the behavior of the transistor structure in the presence of a two-dimensional electron gas. The observed decrease in the transconductance and growth of the threshold voltage with increasing channel island doping size completely corresponds to the ohmic model for transistors with a split gate.
It is shown that this dependence has a quadratic character, namely, when the length of the alloying island is increased by a factor of N2, the corresponding decrease in the steepness of the transistor will be proportional to N times.
SGMOS CHARACTERISTICS UNDER EXTREME THERMAL CONDITIONS
The general change in the I–V characteristics of transistors with increasing temperature is largely due not only to a decrease in the steepness corresponding to the dependences shown in Fig. 3 and Fig. 4. Fig. 5 shows the dependence of the change in runoff characteristics with an increase in temperature to 500 °K.
The shift of the I–V characteristics can be explained by the presence in the model of boundary delta-like changes in the impurity concentration, as shown in Fig. 2, which in turn can serve as a source of a number of high-temperature effects, which could disturb the processes of normal operations of the transistors [12–14]. In particular, for a sufficiently high field strength near the drain region, the formation of impact ionization effects is possible. The results of the simulation confirm this thesis, as shown in Fig. 6. But this process for SGMOS does not have a linear temperature dependence, in particular for a nominal channel length of 0.25μm, the smallest ionization coefficient occurred at a temperature of 127 °C. This effect is possibly associated with a decrease in carrier mobility in the channel with temperature increase and corresponding to an increase in the ohmic resistance of the channel doping island, which acts as a current-limiting resistor.
In general, the results of the analysis showed that the presence of parasitic n-p-n structures is not catastrophic up to temperatures of 200–250 °C. The channel doping island is not equivalent to the base region of a bipolar transistor for this particular model. The island of doping in the channel can be considered as a damping resistor, which allows changing the I–V characteristics of the transistor, from the compensation of, for example, high-temperature and impact ionization effects.
Thus, a reference model for the analysis of SGMOS transistors was developed and investigated. It is shown that the use of a split gate is quite effective in modulation-doped structures of the PDCFET class [15, 16].
Results of the project enable us to prove that the method of periodically doped channel is a new way of the multigate transistor structure for a number of sensors and transducers, in particular for devices based on surface plasmon resonance (SPR). A reference model for the analysis of SGMOS transistors has been developed and investigated. It is shown that the use of a split gate is quite effective in modulation-doped structures of the PDCFET class. Decrease in the steepness, speed, and change in the I–V characteristics of transistor structures are not catastrophic, up to temperatures of 200–250 °C. High-temperature effects, such as impact-ionization regions do not have a linear temperature dependence, in particular for a nominal channel length of 0.25μm, the lowest impact ionization coefficient occurred at a temperature of 127 °C. This implies the possibility of forming optimal transistor control modes for sensors and analog applications. Accordingly, we can assume the possibility of using these transistor structures in high-temperature electronics, sensors and devices based on the effects of SPR.
This work is supported by Russian Foundation for Basic Research, grant № 14-29-09207.
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