rus
Issue #9/2018
Larionov A. V., Buyakova O. N., Sysoeva O. V.
A High-speed Receiver With Adaptive Auxiliary Clock for High Loss Backplane Channels
A High-speed Receiver With Adaptive Auxiliary Clock for High Loss Backplane Channels
The paper presents a technique that allows finding the optimal position of the phase auxiliary clock signal of the receiver. Based on this technique, the controller has been implemented and integrated into the receiver. The simulation results have shown an increase in the opening of eye diagram by 1.8 % of the unit interval horizontally and 38мВ vertically for 10Gb/s data stream passed through the channel with attenuation −23dB at a frequency 5GHz. The receiver is designed in CMOS 65nm technology and operates from the power source 1V.
Теги: decision-feedback equalizer equalizer receiver sign-sign least mean square transceiver бинарный алгоритм наименьших средних квадратов приемник приемопередатчик решающая обратная связь эквалайзер
INTRODUCTION
Electric signal transmitted from transmitter to receiver by cable or printed board, degrades due to a number of reasons. The main physical effects affecting the signal propagation are the following: skin effect, dielectric absorption, reflectance, crosstalk noise, electromagnetic interaction. The rate of degradation of the transmitted signal varies depending on magnitude of these effects in the channel. Consequently, the receiver whose main task is to restore the input signal integrity and to synchronize it with the internal timing system should possess wide range tolerance towards indicated above physical effects. For attaining this goal, the receiver utilizes a number of adaptive algorithms [1–4] performing its adjustment to a particular channel.
The signal attenuation caused by its propagation in the channel results in intersymbol interference (ISI). To compensate for intersymbol interference, the receiver contains a set of controllable equalizers. The greater the ISI and the speed of input data are, the more important is the accuracy of equalizer coefficients calculations. The aim of this work is to improve the accuracy of calculation of the receiver equalizer coefficients.
An important factor affecting the accuracy of coefficients calculations is an approach to latching data at primary latches of the receiver. There are two main approaches to the problem. In the first case [1–2] the receiver performs sampling at the moments of data transitions from zero into unit and back (edge-based equalization). Since these samplings are also required for retiming between input data and clock signals of the receiver, this approach saves considerable amount of power. But horizontal bouncing of input signal alongside with ISI has a number of additional noise sources that affect the accuracy of calculations. The second approach [3–4] is based on comparison of vertical data swing with adjustable reference voltage (level-based equalization), making it possible to fix more relevant information, because vertical noise is smaller. Though this method is more power-consuming, it is more efficient for channels with large attenuation coefficient.
The accuracy of calculation is also affected by clock signal position that performs sampling. The method for searching optimal phase position has been proposed in [5]. However the algorithm of data processing used while calculating equalizer’s coefficients in the receiver is based on scanning the eye diagram (BER-based receiver). This algorithm does not permit using equalizer with decision-feedback (DFE) higher than 1st order, because coefficients calculation for higher orders is not obvious. This decreases the receiver’s tolerance to possible nonlinearities in the channel, thus limiting its application.
In Section 2 this problem is formulated in detail and a methodology of its solution is presented. Section 3 gives general architecture of the receiver and its hardware implementation for auxiliary clock signal adaptive phase adjustment is described. Section 4 presents the results of modelling as well as comparative analysis.
THE PROBLEM AND METHODS OF ITS SOLUTION
For understanding the core of the problem, it is necessary to examine the operation of DFE, the main block of the receiver containing first latches on the path of the output signal. Fig. 1 presents a scheme of high-speed DFE [6] used in the receiver. With the aim of increasing the data processing rate, the equalizer includes two parallel identical pipelines operating at half-rate. One of them is used for processing even (EVEN), the other — for processing odd (ODD) impulses of input data sequence. Let us describe for simplicity the operation of only EVEN pipeline.
Signal z(n), possessing specified portion of ISI, arrives at DFE input, where n is time interval corresponding to one unit interval (UI). For EVEN pipeline only even data are of interest. The input signal of adder weven(2n) is a retrieved signal obtained by means of subtraction feed-back product from input signal:
Eqn001.eps
where h(k) is weighting coefficient for each order of equalizer.
To adjust weighting coefficients it is necessary to determine error e(n). For this purpose the equalizer contains embedded comparators performing comparison of the current level of adder’s output signal with threshold level h(0). Since this system is high-speed, each pipeline has only one comparator to reduce adder’s load. The EVEN pipeline is checking up positive data (units), and the ODD pipeline ODD is checking up negative data (zeros). For this purpose threshold level h(0) at comparator input in EVEN pipeline is supplied directly, and in ODD pipeline inversely. Error in the ODD pipeline can be determined by the following equation:
Eqn002.eps
Fig. 2 shows a diagram of EVEN pipeline signals after convergence of all algorithms used by the receiver. Information is fixed by three clock signals. CLKD fixes signal deven(2n) by its centre, forming initial data transmitted by the channel. CLKB fixes signal deven(2n) at the moment of performing switching operation, forming data necessary for the input signal synchronization with the internal system clock. CLKA fixes signal eeven(2n) by its centre, forming data necessary to restore input signal integrity. At the moment of sampling by CLKD swing of deven(2n) signal will correspond to reference level h(0), and at the moment of sampling by CLKA swing of eeven(2n) signal will equal zero.
From Fig. 2 one can see that wrong position of auxiliary clock signal CLKA will cause error Δe. Therefore, values of weighting coefficients h(k) will be not optimal, thus reducing the system efficiency of restoring the input signal integrity. There exists a number of reasons causing errors:
1) the CLKA clock signal position is determined by quadrature to CLKB, that is their phases are 90° shifted relative to each other. This quadrature may be disturbed, for example, due to technological scatter, as is shown on Fig. 3;
2) the validity of CLKB phase is also not guaranteed. The CLKB displacement from its ideal position has been demonstrated in [7]. The reason lies in a possible asymmetrical distribution of input signal determined jitter;
3) delays of comparator and buffer at Fig. 1 are not identical. Time of propagation from weven(2n) to deven(2n) and to eeven(2n) may be different;
4) there may be data correlation with noise at global “ground” and “power” buses. This may cause asymmetry in differential signal.
The methodology of searching the optimal phase of auxiliary clock signal CLKA proposed in the research is based on threshold level h(0) monitoring. Due to error Δe presented on Fig. 2 the ISI value of input signal (z(n)) registered by the system will seem greater than it is in reality. The total h(k) value will be overestimated, and h(0) value will be underestimated. The essence of this methodology reduces the search of maximum value, hMAX(0), by means of forced variation of CLKA phase in the range overlapping possible deviations from the ideal position. The CLKA phase position where threshold voltage h(0) will be maximal, implies that error e0 has minimal value and coefficients h(k) are maximally close to optimal values. Due to this approach coefficients h(k) do not depend on:
1) the relation of phase CLKA to phase CLKB;
2) the position of phase CLKB relative to input signal;
3) the comparator and buffer delays relation.
Possible asymmetry of input differential signal is also taken into consideration. In this methodology CLKA phase correlates with threshold level h(0) and weighting coefficients h(k), which are calculated using binary algorithm of least square means (SSLMS). Therefore, as opposed to [5], there appears an opportunity of utilizing DFE of arbitrary order, thus increasing tolerance of the receiver to possible nonlinearities in the channel.
RECEIVER WITH PHASE CONTROLLER FOR AUXILIARY CLOCK SIGNAL
Fig. 4 presents typical receiver architecture. The input path consists of TERM, VGA and CTLE blocks. The TERM block matches the receiver input with the channel and the transmitter, providing sufficient level of electrostatic protection and adjusting the constant component level. Automatic VGA amplification adjustment provides optimal swing, and linear CTLE equalizer compensates for ISI in the middle part of input signal frequency spectrum. Then the signal is directed at DFE input consisting of three paths: Boundary, Data and Auxiliary, clocked by CLKB, CLKD and CLKA, respectively. The block is able to compensate for non-linear attenuation of input signal without noise and cross talks amplification. Then fixed data are demultiplexed and processed in low frequency mode in the block of retiming (CDR) and in the block of equalizer coefficients control using SSLMS. The CDR block forms control codes BCode, DCode and ACode for three independent interpolators PI, tuning frequency and phase of clock signals CLKB, CLKD and CLKA. Interpolators operate from high frequency reference quadrature clock signal CLKI/CLKQ, supplied from phase-lock-loop frequency control block PLL. DQC block restores duty ratio and quadrature, facilitating improvement of interpolators linearity. SSLMS forms control codes VGACode, CTLECode, DFECode, adjusting VGA ampliude, depth of CTLE equalizer, threshold value and DFE weighting coefficients, constant component, etc.
Phase controller of auxiliary clock signal CLKA, embedded in this receiver, is called AACC and will be an intermediary between SSLMS and CDR, as is shown on Fig. 5.
Block SSLMS uses de-multiplexed data from Auxiliary and Data. SSLMS is based on equation for adjusting threshold level:
Eqn003.eps
and DFE coefficients:
Eqn004.eps
where µ is transfer coefficient, and sign[e(n)] is sign of error.
The block diagram of CDR is shown on Fig. 6. The block consists of binary phase detector PD, majority voter MV, integral-proportional filter PIF, phase shift former SHIFT and decoder TC. Using de-multiplexed data from Boundary and Data, phase detector selects information about shift direction of the receiver clock impulse. The majority voter performs decimation, making it possible to reduce frequency of data processing and to mitigate temporary restrictions for PIF. The digital filter accumulates information for controlling phase and frequency of clock signals in integral and proportional paths, respectively. Coefficients KI and KP set bandwidths in these paths. Block TC decodes binary code from PIF output in thermo-cod BCode, DCode, ACode clear to interpolators. Coefficients KD and KA set shifts, DCode and ACode respectively, relative to BCode.
In the normal mode of CDR operation all its coefficients are constants. When AACC controller is in active state, coefficient KA will become variable value, varying CLKA phase. Value h(n, 0), formed by SSLMS block, is used by controller as input data for estimating the direction of CLKA shift. The general principle of AACC controller operation is presented in Table 1. On each step the controller analyses the aggregate of three variables: current value of threshold level h(n, 0), previous value of threshold level h(n – 1, 0) and sign of increment coefficient sign[а(n – 1)] at the previous step. Proceeding from these data, the current sign of increment coefficient sign[а(n)] is formed, increasing or decreasing the value of KA(n) coefficient. If h(n, 0) > h(n – 1, 0) or h(n, 0) = h(n – 1, 0), then sign of increment coefficient does not change. If h(n, 0) < h(n – 1, 0), then sign of increment coefficient is changed to the opposite. Note that KA coefficient is changing on each step, even if h(n, 0) = h(n – 1, 0), making it possible to stimulate state machine to perform the search.
Fig. 7 presents AACC implementation. The comparator compares two 7-bit codes, current and previous threshold levels, h(n, 0) and h(n – 1, 0), respectively. Logical zero or unit of increment coefficient a(n) reflect its sign, depending on the result at the comparator output and previous value a(n – 1). Coefficient KIA specifies the controller’s bandwidth. Data are accumulated in 24-bit character count unit with saturation, where seven high-order bits reflect coefficient KA(n). Let us note two moments. First, in this implementation of the receiver, clock signals frequencies, clocking CDR and SSLMS, are identical or multiple of each other, which does not cause any problems with data synchronization. Second, the controller is activated upon convergence of CDR and SSLMS blocks and, after a certain time period stops and fixes KA.
THE RESULTS OF SIMULATION
For checking the efficiency of the proposed method, the receiver simulation with switched off and switched on controller of auxiliary clock signal phase control has been performed. To that end, 10Gb/s differential signal is formed by the transmitter and transmitted through the channel with –23dB attenuation at Nyquist frequency (Fig. 8) and supplied at the receiver input. The receiver equalizer is switched off, and the deletion of intersymbol interference is performed only by the receiver equalizers. The phase of auxiliary clock signal CLKA is artificially shifted by 12 degrees from the ideal position. The results of the receiver modelling on Fig. 9 indicate that the controller activation permits increasing the “eye” opening by 1.8ps (1.8 % from 100ps unit interval) horizontally and by 38mV vertically.
CONCLUSION
This paper offers a method that enables one to find out an optimal phase position of auxiliary clock signal in the receiver. Basing on this method a new controller has been implemented and integrated into the receiver. The results of simulation indicate an increase by 1.8 % in the eye diagram opening from unit interval horizontally and by 38mV vertically. The receiver is implemented using 65nm CMOS technology and operates at 1V rated voltage.
REFERENCES
1. Payne R., Landman P., Bhakta B. et al. A 6.25-Gb/s Binary Transceiver in 0.13-µm CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels // IEEE Journal of Solid-State Circuits. 2005. Vol. 40. № 12, pp. 2646–2657.
2. Savoj J., Hsieh K., An F. et al. A Low-power 0.5–6.6Gb/s Wireline Transceiver Embedded in Low-cost 28nm FPGAs // IEEE Journal of Solid-State Circuits. 2013. Vol. 48. № 11, pp. 2582–2594.
3. Pozzoni M., Erba S., Viola P. et al. A Multi-standard 1.5 to 10Gb/s Latch-based 3-tap DFE Receiver with a SSC Tolerant CDR for Serial Backplane Communication // IEEE Journal of Solid-State Circuits. 2009. Vol. 44. № 4, pp. 1306–1315.
4. Zhong F., Quan S., Liu W. et al. A 1.0625 ~14.025Gb/s Multi-media Transceiver With Full-rate Source-series-terminated Transmit Driver and Floating-tap Decision-feedback Equalizer in 40nm CMOS // IEEE Journal of Solid-State Circuits. 2011. Vol. 46. № 12, pp. 3126–3139.
5. Won H., Lee J., Yoon T. et al. A 28-Gb/s Receiver With Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-tracking Eye-opening Monitor // IEEE Journal of Transactions on Circuit and Systems-I. 2017. Vol. 64. № 3, pp. 664–674.
6. Larionov A. V. Ekvalaizer s reshayushchei obratnoi svyaz'yu i aktivnoi induktivnost'yu dlya vysokoskorostnogo priemnika // VII Vserossiiskaya nauchno-tekhnicheskaya konferentsiya “Problemy razrabotki perspektivnykh mikro- i nanoelektronnykh sistem-2016 (MES-2016)” Sbornik nauchnykh trudov. / Pod red. A. L. Stempkovskogo — M.: IPPM RAN, 2016. Chast' III — P. 2–7.
7. Fucuda K., Yamashita H., Yuki M. et al. An 8Gb/s Transceiver With 3x-oversampling 2-threshold Eye-tracking CDR Circuit for −36.8dB Loss Backplane // IEEE International Solid-State Circuits Conference. 2008. SES. 5, pp. 98–99.
Electric signal transmitted from transmitter to receiver by cable or printed board, degrades due to a number of reasons. The main physical effects affecting the signal propagation are the following: skin effect, dielectric absorption, reflectance, crosstalk noise, electromagnetic interaction. The rate of degradation of the transmitted signal varies depending on magnitude of these effects in the channel. Consequently, the receiver whose main task is to restore the input signal integrity and to synchronize it with the internal timing system should possess wide range tolerance towards indicated above physical effects. For attaining this goal, the receiver utilizes a number of adaptive algorithms [1–4] performing its adjustment to a particular channel.
The signal attenuation caused by its propagation in the channel results in intersymbol interference (ISI). To compensate for intersymbol interference, the receiver contains a set of controllable equalizers. The greater the ISI and the speed of input data are, the more important is the accuracy of equalizer coefficients calculations. The aim of this work is to improve the accuracy of calculation of the receiver equalizer coefficients.
An important factor affecting the accuracy of coefficients calculations is an approach to latching data at primary latches of the receiver. There are two main approaches to the problem. In the first case [1–2] the receiver performs sampling at the moments of data transitions from zero into unit and back (edge-based equalization). Since these samplings are also required for retiming between input data and clock signals of the receiver, this approach saves considerable amount of power. But horizontal bouncing of input signal alongside with ISI has a number of additional noise sources that affect the accuracy of calculations. The second approach [3–4] is based on comparison of vertical data swing with adjustable reference voltage (level-based equalization), making it possible to fix more relevant information, because vertical noise is smaller. Though this method is more power-consuming, it is more efficient for channels with large attenuation coefficient.
The accuracy of calculation is also affected by clock signal position that performs sampling. The method for searching optimal phase position has been proposed in [5]. However the algorithm of data processing used while calculating equalizer’s coefficients in the receiver is based on scanning the eye diagram (BER-based receiver). This algorithm does not permit using equalizer with decision-feedback (DFE) higher than 1st order, because coefficients calculation for higher orders is not obvious. This decreases the receiver’s tolerance to possible nonlinearities in the channel, thus limiting its application.
In Section 2 this problem is formulated in detail and a methodology of its solution is presented. Section 3 gives general architecture of the receiver and its hardware implementation for auxiliary clock signal adaptive phase adjustment is described. Section 4 presents the results of modelling as well as comparative analysis.
THE PROBLEM AND METHODS OF ITS SOLUTION
For understanding the core of the problem, it is necessary to examine the operation of DFE, the main block of the receiver containing first latches on the path of the output signal. Fig. 1 presents a scheme of high-speed DFE [6] used in the receiver. With the aim of increasing the data processing rate, the equalizer includes two parallel identical pipelines operating at half-rate. One of them is used for processing even (EVEN), the other — for processing odd (ODD) impulses of input data sequence. Let us describe for simplicity the operation of only EVEN pipeline.
Signal z(n), possessing specified portion of ISI, arrives at DFE input, where n is time interval corresponding to one unit interval (UI). For EVEN pipeline only even data are of interest. The input signal of adder weven(2n) is a retrieved signal obtained by means of subtraction feed-back product from input signal:
Eqn001.eps
where h(k) is weighting coefficient for each order of equalizer.
To adjust weighting coefficients it is necessary to determine error e(n). For this purpose the equalizer contains embedded comparators performing comparison of the current level of adder’s output signal with threshold level h(0). Since this system is high-speed, each pipeline has only one comparator to reduce adder’s load. The EVEN pipeline is checking up positive data (units), and the ODD pipeline ODD is checking up negative data (zeros). For this purpose threshold level h(0) at comparator input in EVEN pipeline is supplied directly, and in ODD pipeline inversely. Error in the ODD pipeline can be determined by the following equation:
Eqn002.eps
Fig. 2 shows a diagram of EVEN pipeline signals after convergence of all algorithms used by the receiver. Information is fixed by three clock signals. CLKD fixes signal deven(2n) by its centre, forming initial data transmitted by the channel. CLKB fixes signal deven(2n) at the moment of performing switching operation, forming data necessary for the input signal synchronization with the internal system clock. CLKA fixes signal eeven(2n) by its centre, forming data necessary to restore input signal integrity. At the moment of sampling by CLKD swing of deven(2n) signal will correspond to reference level h(0), and at the moment of sampling by CLKA swing of eeven(2n) signal will equal zero.
From Fig. 2 one can see that wrong position of auxiliary clock signal CLKA will cause error Δe. Therefore, values of weighting coefficients h(k) will be not optimal, thus reducing the system efficiency of restoring the input signal integrity. There exists a number of reasons causing errors:
1) the CLKA clock signal position is determined by quadrature to CLKB, that is their phases are 90° shifted relative to each other. This quadrature may be disturbed, for example, due to technological scatter, as is shown on Fig. 3;
2) the validity of CLKB phase is also not guaranteed. The CLKB displacement from its ideal position has been demonstrated in [7]. The reason lies in a possible asymmetrical distribution of input signal determined jitter;
3) delays of comparator and buffer at Fig. 1 are not identical. Time of propagation from weven(2n) to deven(2n) and to eeven(2n) may be different;
4) there may be data correlation with noise at global “ground” and “power” buses. This may cause asymmetry in differential signal.
The methodology of searching the optimal phase of auxiliary clock signal CLKA proposed in the research is based on threshold level h(0) monitoring. Due to error Δe presented on Fig. 2 the ISI value of input signal (z(n)) registered by the system will seem greater than it is in reality. The total h(k) value will be overestimated, and h(0) value will be underestimated. The essence of this methodology reduces the search of maximum value, hMAX(0), by means of forced variation of CLKA phase in the range overlapping possible deviations from the ideal position. The CLKA phase position where threshold voltage h(0) will be maximal, implies that error e0 has minimal value and coefficients h(k) are maximally close to optimal values. Due to this approach coefficients h(k) do not depend on:
1) the relation of phase CLKA to phase CLKB;
2) the position of phase CLKB relative to input signal;
3) the comparator and buffer delays relation.
Possible asymmetry of input differential signal is also taken into consideration. In this methodology CLKA phase correlates with threshold level h(0) and weighting coefficients h(k), which are calculated using binary algorithm of least square means (SSLMS). Therefore, as opposed to [5], there appears an opportunity of utilizing DFE of arbitrary order, thus increasing tolerance of the receiver to possible nonlinearities in the channel.
RECEIVER WITH PHASE CONTROLLER FOR AUXILIARY CLOCK SIGNAL
Fig. 4 presents typical receiver architecture. The input path consists of TERM, VGA and CTLE blocks. The TERM block matches the receiver input with the channel and the transmitter, providing sufficient level of electrostatic protection and adjusting the constant component level. Automatic VGA amplification adjustment provides optimal swing, and linear CTLE equalizer compensates for ISI in the middle part of input signal frequency spectrum. Then the signal is directed at DFE input consisting of three paths: Boundary, Data and Auxiliary, clocked by CLKB, CLKD and CLKA, respectively. The block is able to compensate for non-linear attenuation of input signal without noise and cross talks amplification. Then fixed data are demultiplexed and processed in low frequency mode in the block of retiming (CDR) and in the block of equalizer coefficients control using SSLMS. The CDR block forms control codes BCode, DCode and ACode for three independent interpolators PI, tuning frequency and phase of clock signals CLKB, CLKD and CLKA. Interpolators operate from high frequency reference quadrature clock signal CLKI/CLKQ, supplied from phase-lock-loop frequency control block PLL. DQC block restores duty ratio and quadrature, facilitating improvement of interpolators linearity. SSLMS forms control codes VGACode, CTLECode, DFECode, adjusting VGA ampliude, depth of CTLE equalizer, threshold value and DFE weighting coefficients, constant component, etc.
Phase controller of auxiliary clock signal CLKA, embedded in this receiver, is called AACC and will be an intermediary between SSLMS and CDR, as is shown on Fig. 5.
Block SSLMS uses de-multiplexed data from Auxiliary and Data. SSLMS is based on equation for adjusting threshold level:
Eqn003.eps
and DFE coefficients:
Eqn004.eps
where µ is transfer coefficient, and sign[e(n)] is sign of error.
The block diagram of CDR is shown on Fig. 6. The block consists of binary phase detector PD, majority voter MV, integral-proportional filter PIF, phase shift former SHIFT and decoder TC. Using de-multiplexed data from Boundary and Data, phase detector selects information about shift direction of the receiver clock impulse. The majority voter performs decimation, making it possible to reduce frequency of data processing and to mitigate temporary restrictions for PIF. The digital filter accumulates information for controlling phase and frequency of clock signals in integral and proportional paths, respectively. Coefficients KI and KP set bandwidths in these paths. Block TC decodes binary code from PIF output in thermo-cod BCode, DCode, ACode clear to interpolators. Coefficients KD and KA set shifts, DCode and ACode respectively, relative to BCode.
In the normal mode of CDR operation all its coefficients are constants. When AACC controller is in active state, coefficient KA will become variable value, varying CLKA phase. Value h(n, 0), formed by SSLMS block, is used by controller as input data for estimating the direction of CLKA shift. The general principle of AACC controller operation is presented in Table 1. On each step the controller analyses the aggregate of three variables: current value of threshold level h(n, 0), previous value of threshold level h(n – 1, 0) and sign of increment coefficient sign[а(n – 1)] at the previous step. Proceeding from these data, the current sign of increment coefficient sign[а(n)] is formed, increasing or decreasing the value of KA(n) coefficient. If h(n, 0) > h(n – 1, 0) or h(n, 0) = h(n – 1, 0), then sign of increment coefficient does not change. If h(n, 0) < h(n – 1, 0), then sign of increment coefficient is changed to the opposite. Note that KA coefficient is changing on each step, even if h(n, 0) = h(n – 1, 0), making it possible to stimulate state machine to perform the search.
Fig. 7 presents AACC implementation. The comparator compares two 7-bit codes, current and previous threshold levels, h(n, 0) and h(n – 1, 0), respectively. Logical zero or unit of increment coefficient a(n) reflect its sign, depending on the result at the comparator output and previous value a(n – 1). Coefficient KIA specifies the controller’s bandwidth. Data are accumulated in 24-bit character count unit with saturation, where seven high-order bits reflect coefficient KA(n). Let us note two moments. First, in this implementation of the receiver, clock signals frequencies, clocking CDR and SSLMS, are identical or multiple of each other, which does not cause any problems with data synchronization. Second, the controller is activated upon convergence of CDR and SSLMS blocks and, after a certain time period stops and fixes KA.
THE RESULTS OF SIMULATION
For checking the efficiency of the proposed method, the receiver simulation with switched off and switched on controller of auxiliary clock signal phase control has been performed. To that end, 10Gb/s differential signal is formed by the transmitter and transmitted through the channel with –23dB attenuation at Nyquist frequency (Fig. 8) and supplied at the receiver input. The receiver equalizer is switched off, and the deletion of intersymbol interference is performed only by the receiver equalizers. The phase of auxiliary clock signal CLKA is artificially shifted by 12 degrees from the ideal position. The results of the receiver modelling on Fig. 9 indicate that the controller activation permits increasing the “eye” opening by 1.8ps (1.8 % from 100ps unit interval) horizontally and by 38mV vertically.
CONCLUSION
This paper offers a method that enables one to find out an optimal phase position of auxiliary clock signal in the receiver. Basing on this method a new controller has been implemented and integrated into the receiver. The results of simulation indicate an increase by 1.8 % in the eye diagram opening from unit interval horizontally and by 38mV vertically. The receiver is implemented using 65nm CMOS technology and operates at 1V rated voltage.
REFERENCES
1. Payne R., Landman P., Bhakta B. et al. A 6.25-Gb/s Binary Transceiver in 0.13-µm CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels // IEEE Journal of Solid-State Circuits. 2005. Vol. 40. № 12, pp. 2646–2657.
2. Savoj J., Hsieh K., An F. et al. A Low-power 0.5–6.6Gb/s Wireline Transceiver Embedded in Low-cost 28nm FPGAs // IEEE Journal of Solid-State Circuits. 2013. Vol. 48. № 11, pp. 2582–2594.
3. Pozzoni M., Erba S., Viola P. et al. A Multi-standard 1.5 to 10Gb/s Latch-based 3-tap DFE Receiver with a SSC Tolerant CDR for Serial Backplane Communication // IEEE Journal of Solid-State Circuits. 2009. Vol. 44. № 4, pp. 1306–1315.
4. Zhong F., Quan S., Liu W. et al. A 1.0625 ~14.025Gb/s Multi-media Transceiver With Full-rate Source-series-terminated Transmit Driver and Floating-tap Decision-feedback Equalizer in 40nm CMOS // IEEE Journal of Solid-State Circuits. 2011. Vol. 46. № 12, pp. 3126–3139.
5. Won H., Lee J., Yoon T. et al. A 28-Gb/s Receiver With Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-tracking Eye-opening Monitor // IEEE Journal of Transactions on Circuit and Systems-I. 2017. Vol. 64. № 3, pp. 664–674.
6. Larionov A. V. Ekvalaizer s reshayushchei obratnoi svyaz'yu i aktivnoi induktivnost'yu dlya vysokoskorostnogo priemnika // VII Vserossiiskaya nauchno-tekhnicheskaya konferentsiya “Problemy razrabotki perspektivnykh mikro- i nanoelektronnykh sistem-2016 (MES-2016)” Sbornik nauchnykh trudov. / Pod red. A. L. Stempkovskogo — M.: IPPM RAN, 2016. Chast' III — P. 2–7.
7. Fucuda K., Yamashita H., Yuki M. et al. An 8Gb/s Transceiver With 3x-oversampling 2-threshold Eye-tracking CDR Circuit for −36.8dB Loss Backplane // IEEE International Solid-State Circuits Conference. 2008. SES. 5, pp. 98–99.
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