rus
Issue #9/2018
Matveev Dmitriy V.
Peculiarities of Developing Low-power ADC With Successive Approximation Register
Peculiarities of Developing Low-power ADC With Successive Approximation Register
This work examines an approach for designing low-power analog-to-digital converters with successive approximation register, as well as offers the implementation of successive approximation register for ADC with maximal digital capacity of 12 bits using 65nm TSMC technology.
Теги: adc with successive approximation register designing low-power circuits ацп последовательного приближения проектирование малопотребляющих схем
INTRODUCTION
Despite modern digitalization trend in almost all the spheres of human activity, there always exists a certain barrier between analogue and digital worlds. That is why analog-to-digital converters (ADC) constitute integral part of virtually any digital system, interacting with environment by means of different sensors. Frequently such sensors like temperature-sensitive element do not require high conversion rate. This enables one to select convenient ADC architecture for application in each specific case.
ARCHITECTURE
In this work complex functional ADC block is a constituent part of a very large scale integration circuit (VLSI) belonging to System-on-Crystal (SoC) class. Requirements for maximum admissible power consumption, capability to select a mode of power consumption and maximum admissible occupied area have been imposed on this block. Since high rate and accuracy of conversion are not required, those requirements are met by the converter architecture with successive approximation. It is one of the most popular architectures used today. As opposed to flash and pipelined ADCs, the converter with successive approximation has only one parameter, which results in significantly less power consumption and simpler implementation as compared with sigma-delta ADC converter [1].
Its operation is based on sequential comparison of measured value with 1/2, 1/4, 1/8 etc. parts of maximum reference voltage value. This enables N-bit ADC with successive approximation to perform the whole conversion process in N successive steps. The standard architecture of converter with successive approximation register, also called as ADC with bitwise balancing, comprises a sampling and holding device, comparator, digital-to-analog converter (DAC) and successive approximation register.
The sampling and holding device virtually in all modifications contains a buffer based on operational amplifier for maintaining accurate signal value, which contributes to the converter total power consumption. One of the ways of power consumption reduction is application of digital-to-analog converter circuit with embedded sampling and holding device [2]. Fig. 1 shows the simplified ADC structure with DAC, also performing functions of sampling and holding device. In this case not DAC output potential approaches the stored input potential step by step, but the stored potential approaches half of the reference voltage value (“virtual zero”).
In practice, the occupied area is determined by the device biggest element, in our case it is binary weighted capacitor array. As differential structure has twice as large area compared to single pole area, the single pole area has been chosen for providing minimal possible occupied area.
The successive approximation register (SAR) performs control functions (using analogue switches), processes comparator signal and issues digital code upon converting the cycle termination. As single pole power supply is used, a positive potential is the middle point of the measuring range. So the values obtained in the “negative” range have to be inverted. In this research the successive approximation register enables controlling the bits number in output words, thus changing the number of cycles necessary for one conversion. An additional peculiarity is a possibility of setting the duration of sampling.
It is important to provide the user with opportunity to control the mode of operation. The SoC must possess versatility in power consumption settings. Most commonly used methods for reducing power consumption are gating techniques for clock signal and building the system of disconnecting power domains. It is necessary to provide several modes for each block operation within SoC to reveal trade-off between saved power and time necessary for switching on and off respective blocks. Gating technique for clock signal is used in all modern devices by default.
Another efficient way to reduce power consumption for static and dynamic power is shutting down power supply to spare blocks. Additional internal power and ground buses are created in the system. A connection between internal and external buses is provided through switches. In such a way, upon receiving signal internal buses become disconnected and power supply does not reach the respective block. If this block is required in operating condition, its power supply returns back by signal removal from the respective switch [3]. Structures Common Power Format based on TCL language syntax enables describing multi-domain systems with various supply voltages and modes of operation.
This converter has been developed for operating in two power domains: 3.3V for analogue blocks and 1.2V for digital blocks with three modes of operation: nominal operative mode, shutting down digital block of power supply, sleep mode (full power supply shutting down). At the moments when the blocks power supply is switched off, output signals of these blocks reside in undefined state, because at the moment of power supply being switched off it is necessary to fixate some value by means of insulating cells. So, the process of switching off power includes the following steps: the locking is stopped, output buses of switched off blocks (for example, all in “zero” state) are fixed using insulating cells and shutting down internal buses supplying power to domains. While planning the clock signal gating it is also necessary to use clock signal for gating analogue blocks. Due to this technique, the reduction of power consumption may attain 95 % of power value in inactive mode [4].
MODELLING
Figures 2–3 show the data obtained by modelling. In Fig. 2а one can see how the output voltage of capacitors array comes closer to half of the reference voltage value. Fig. 3 shows the process of stage by stage switching power supply off. First of all, digital blocks power supply is switched off, and then power supply of analogue blocks is switched off. When power supply of digital blocks is switched off, there is a jump attaining 100nW on the diagram of consumed power, but for better visualization of the rest of the diagram this spike has been truncated. The results of modelling clearly demonstrate the opportunities of methods for reducing power consumption. In the considered case power consumed by DAC is reduced by 3 orders of magnitude (from ≈ 1.2microW down to ≈ 8nW), digital logic is reduced by a factor of 5–7 (from ≈ 6.8nW down to ≈ 1.1nW).
CONCLUSION
The research deals with developing the successive approximation register for ADC with maximal digital capacity 12 bit using 65nm TSMC technology, as well as modelling at transistor level. Average power consumed by the register and finite state machine in active mode constitutes 4.5microW.
REFERENCES
1. Paul G. A. “Jespers Integrated Converters D to A and A to D ARCHITECTURES, ANALYSIS AND SIMULATION” / 2001. Oxford University Press Inc. 2004. P. 76–87.
2. Ravi Kumar K. “A 12 bit 50MSPS Low Power SAR ADC in UMC 65nm Technology” / 2017. Signal Processing, Communication, Power and Embedded System (SCOPES), 2016.
3. Panda P. R. “Basic Low Power Digital Design” / 2010. Springer US — 2010. P. 11–39.
4. Rakesh Chadha, Bhasker J. “An ASIC Low Power Primer” / 2013. Springer US — 2013. P. 134–135.
Despite modern digitalization trend in almost all the spheres of human activity, there always exists a certain barrier between analogue and digital worlds. That is why analog-to-digital converters (ADC) constitute integral part of virtually any digital system, interacting with environment by means of different sensors. Frequently such sensors like temperature-sensitive element do not require high conversion rate. This enables one to select convenient ADC architecture for application in each specific case.
ARCHITECTURE
In this work complex functional ADC block is a constituent part of a very large scale integration circuit (VLSI) belonging to System-on-Crystal (SoC) class. Requirements for maximum admissible power consumption, capability to select a mode of power consumption and maximum admissible occupied area have been imposed on this block. Since high rate and accuracy of conversion are not required, those requirements are met by the converter architecture with successive approximation. It is one of the most popular architectures used today. As opposed to flash and pipelined ADCs, the converter with successive approximation has only one parameter, which results in significantly less power consumption and simpler implementation as compared with sigma-delta ADC converter [1].
Its operation is based on sequential comparison of measured value with 1/2, 1/4, 1/8 etc. parts of maximum reference voltage value. This enables N-bit ADC with successive approximation to perform the whole conversion process in N successive steps. The standard architecture of converter with successive approximation register, also called as ADC with bitwise balancing, comprises a sampling and holding device, comparator, digital-to-analog converter (DAC) and successive approximation register.
The sampling and holding device virtually in all modifications contains a buffer based on operational amplifier for maintaining accurate signal value, which contributes to the converter total power consumption. One of the ways of power consumption reduction is application of digital-to-analog converter circuit with embedded sampling and holding device [2]. Fig. 1 shows the simplified ADC structure with DAC, also performing functions of sampling and holding device. In this case not DAC output potential approaches the stored input potential step by step, but the stored potential approaches half of the reference voltage value (“virtual zero”).
In practice, the occupied area is determined by the device biggest element, in our case it is binary weighted capacitor array. As differential structure has twice as large area compared to single pole area, the single pole area has been chosen for providing minimal possible occupied area.
The successive approximation register (SAR) performs control functions (using analogue switches), processes comparator signal and issues digital code upon converting the cycle termination. As single pole power supply is used, a positive potential is the middle point of the measuring range. So the values obtained in the “negative” range have to be inverted. In this research the successive approximation register enables controlling the bits number in output words, thus changing the number of cycles necessary for one conversion. An additional peculiarity is a possibility of setting the duration of sampling.
It is important to provide the user with opportunity to control the mode of operation. The SoC must possess versatility in power consumption settings. Most commonly used methods for reducing power consumption are gating techniques for clock signal and building the system of disconnecting power domains. It is necessary to provide several modes for each block operation within SoC to reveal trade-off between saved power and time necessary for switching on and off respective blocks. Gating technique for clock signal is used in all modern devices by default.
Another efficient way to reduce power consumption for static and dynamic power is shutting down power supply to spare blocks. Additional internal power and ground buses are created in the system. A connection between internal and external buses is provided through switches. In such a way, upon receiving signal internal buses become disconnected and power supply does not reach the respective block. If this block is required in operating condition, its power supply returns back by signal removal from the respective switch [3]. Structures Common Power Format based on TCL language syntax enables describing multi-domain systems with various supply voltages and modes of operation.
This converter has been developed for operating in two power domains: 3.3V for analogue blocks and 1.2V for digital blocks with three modes of operation: nominal operative mode, shutting down digital block of power supply, sleep mode (full power supply shutting down). At the moments when the blocks power supply is switched off, output signals of these blocks reside in undefined state, because at the moment of power supply being switched off it is necessary to fixate some value by means of insulating cells. So, the process of switching off power includes the following steps: the locking is stopped, output buses of switched off blocks (for example, all in “zero” state) are fixed using insulating cells and shutting down internal buses supplying power to domains. While planning the clock signal gating it is also necessary to use clock signal for gating analogue blocks. Due to this technique, the reduction of power consumption may attain 95 % of power value in inactive mode [4].
MODELLING
Figures 2–3 show the data obtained by modelling. In Fig. 2а one can see how the output voltage of capacitors array comes closer to half of the reference voltage value. Fig. 3 shows the process of stage by stage switching power supply off. First of all, digital blocks power supply is switched off, and then power supply of analogue blocks is switched off. When power supply of digital blocks is switched off, there is a jump attaining 100nW on the diagram of consumed power, but for better visualization of the rest of the diagram this spike has been truncated. The results of modelling clearly demonstrate the opportunities of methods for reducing power consumption. In the considered case power consumed by DAC is reduced by 3 orders of magnitude (from ≈ 1.2microW down to ≈ 8nW), digital logic is reduced by a factor of 5–7 (from ≈ 6.8nW down to ≈ 1.1nW).
CONCLUSION
The research deals with developing the successive approximation register for ADC with maximal digital capacity 12 bit using 65nm TSMC technology, as well as modelling at transistor level. Average power consumed by the register and finite state machine in active mode constitutes 4.5microW.
REFERENCES
1. Paul G. A. “Jespers Integrated Converters D to A and A to D ARCHITECTURES, ANALYSIS AND SIMULATION” / 2001. Oxford University Press Inc. 2004. P. 76–87.
2. Ravi Kumar K. “A 12 bit 50MSPS Low Power SAR ADC in UMC 65nm Technology” / 2017. Signal Processing, Communication, Power and Embedded System (SCOPES), 2016.
3. Panda P. R. “Basic Low Power Digital Design” / 2010. Springer US — 2010. P. 11–39.
4. Rakesh Chadha, Bhasker J. “An ASIC Low Power Primer” / 2013. Springer US — 2013. P. 134–135.
Readers feedback
