rus
Issue #9/2018
Novozhilov E. A.
Implementing SpaceWire Interface in Microprocessors Manufactured by SRISA RAS for Space Applications
Implementing SpaceWire Interface in Microprocessors Manufactured by SRISA RAS for Space Applications
Reported building blocks for SpaceWire interface in family of chips for space applications, developed by SRISA.
The SRISA RAS has developed a series of microcircuits for space application. This series includes a control processor, a redundant/back-up hardened processor, a processor supporting previously developed modules with PCI interface, SpaceWire interface switch unit. These microcircuits have a unified implementation of SpaceWire subsystem, making it possible to build systems basing on this interface. Microcircuits manufactured by 250nm geometry size technology at domestic factories utilize silicon on insulator wafers. Microcircuits are assembled in hermetic cerametallic packages. The paper highlights the main solutions for SpaceWire subsystem implementation.
SpaceWire interface was custom-made for the European Space Agency (ЕSА) to unify communication between different devices in space vehicles. The ESA issued a number of standards to provide compatibility between devices utilizing this interface.
The unified SpaceWire subsystem developed by the SRISA RAS meets the requirements of these standards. Fig. 1 presents a block diagram of SpaceWire subsystem.
SpaceWire subsystem consists of a routing device, external interface ports connected to it and system interface port equipped with direct memory access controllers for receiving and transmitting packets.
The routing device consists of a non-blocking switchboard and a switching table. It produces switching and packets forwarding inside SpaceWire network, has several switching ports, one of them being a system interface port. External ports are compatible with ЕКА ECSS-E-ST-50-12C standard. Control and state registers are used for tuning, controlling and checking SpaceWire subsystem from the side of central processor.
Characteristics of Main SpaceWire Subsystem Devices
Interface Port:
The interface port corresponds to ЕКА ECSS-E-ST-50-12C standard.
The port uses differential signals (LVDS), whose electrical characteristics correspond to ANSI/TIA/EIA-644 standard.
Port signals encoding is carried out in accordance with IEEE 1355-1995 standard.
Direct Memory Access Controller:
Consists of receiving and transmitting channels. The channels operate independently of each other.
Provides data transmission from address space of computation system into SpaceWire network and backwards without central processor participation.
Software model allowing an opportunity of ulilizing RMAP protocol commands was built up in compliance with ЕКА ECSS-E-ST-50-52C standard. It supports protocol identification in accordance with ЕКА ECSS-E-ST-50-51C standard. Maximum length of transmitted and received data packets is 16Мb.
Performs the role of master device on the bus of computing system.
Switchboard:
Non-blocking structure permits connecting any input port with any free output port independently of other ports operation;
Supports several ports, one of which being a system interface port;
Supports logical addressing; in this case the switching table is used;
Supports group adaptive routing;
Supports broadcast and multicast means of packets transfer.
The author considers that in this research the following provisions and results are novel: unified hardware tools have been developed for building SpaceWire subsystem used in microcircuits for space application.
REFERENCES
1. IEEE Computer Society, “IEEE Standard for Heterogeneous Interconnect (HIC) (Low-Cost, Low-Latency Scalable Serial Interconnect for Parallel System Construction)”, IEEE Standard 1355-1995.
2. IEEE Computer Society, “IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI)”, IEEE Standard 1596.3-1996.
3. ESA Requirements and Standards Division. “SpaceWire. Links, Nodes, Routers and Networks”, ECSS-E-ST-50-12C.
4. ESA Requirements and Standards Division. “SpaceWire Protocol Identification”, ECSS-E-ST-50-51C.
5. ESA Requirements and Standards Division. “SpaceWire. Remote Memory Access Protocol”, ECSS-E-ST-50-52C.
SpaceWire interface was custom-made for the European Space Agency (ЕSА) to unify communication between different devices in space vehicles. The ESA issued a number of standards to provide compatibility between devices utilizing this interface.
The unified SpaceWire subsystem developed by the SRISA RAS meets the requirements of these standards. Fig. 1 presents a block diagram of SpaceWire subsystem.
SpaceWire subsystem consists of a routing device, external interface ports connected to it and system interface port equipped with direct memory access controllers for receiving and transmitting packets.
The routing device consists of a non-blocking switchboard and a switching table. It produces switching and packets forwarding inside SpaceWire network, has several switching ports, one of them being a system interface port. External ports are compatible with ЕКА ECSS-E-ST-50-12C standard. Control and state registers are used for tuning, controlling and checking SpaceWire subsystem from the side of central processor.
Characteristics of Main SpaceWire Subsystem Devices
Interface Port:
The interface port corresponds to ЕКА ECSS-E-ST-50-12C standard.
The port uses differential signals (LVDS), whose electrical characteristics correspond to ANSI/TIA/EIA-644 standard.
Port signals encoding is carried out in accordance with IEEE 1355-1995 standard.
Direct Memory Access Controller:
Consists of receiving and transmitting channels. The channels operate independently of each other.
Provides data transmission from address space of computation system into SpaceWire network and backwards without central processor participation.
Software model allowing an opportunity of ulilizing RMAP protocol commands was built up in compliance with ЕКА ECSS-E-ST-50-52C standard. It supports protocol identification in accordance with ЕКА ECSS-E-ST-50-51C standard. Maximum length of transmitted and received data packets is 16Мb.
Performs the role of master device on the bus of computing system.
Switchboard:
Non-blocking structure permits connecting any input port with any free output port independently of other ports operation;
Supports several ports, one of which being a system interface port;
Supports logical addressing; in this case the switching table is used;
Supports group adaptive routing;
Supports broadcast and multicast means of packets transfer.
The author considers that in this research the following provisions and results are novel: unified hardware tools have been developed for building SpaceWire subsystem used in microcircuits for space application.
REFERENCES
1. IEEE Computer Society, “IEEE Standard for Heterogeneous Interconnect (HIC) (Low-Cost, Low-Latency Scalable Serial Interconnect for Parallel System Construction)”, IEEE Standard 1355-1995.
2. IEEE Computer Society, “IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI)”, IEEE Standard 1596.3-1996.
3. ESA Requirements and Standards Division. “SpaceWire. Links, Nodes, Routers and Networks”, ECSS-E-ST-50-12C.
4. ESA Requirements and Standards Division. “SpaceWire Protocol Identification”, ECSS-E-ST-50-51C.
5. ESA Requirements and Standards Division. “SpaceWire. Remote Memory Access Protocol”, ECSS-E-ST-50-52C.
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