A Block of Digital Correction for a High Performance Analog-to-digital Converter
The main sources of inaccuracy are as follows:
• bias voltage of comparator and deviations of reference voltages (main cause);
• bias voltage of operational amplifier;
• finiteness of direct current amplification in operational amplifier;
• finiteness of amplification band in operational amplifier;
• spread of capacity values of DAC capacitors.
The algorithm of digital correction is based on encoding with redundant significant digit (RSD-coding). Fig. 2 shows the structure of calibration block channel. This block is structurally divided into four parts. Four most significant cascades are calibrated, including one 3.5-bit, two 2.5-bit and one 1.5-bit. Least significant 1.5-bit cascades have only a minor effect on conversion accuracy that is why there is no need to calibrate them. The arithmetic unit consists of single-type digital processors for processing signals (DPPS), control finite state machine and block for computing coefficient (see Fig. 3). As the required computing is impossible to be done in one clock period, it is necessary to organize a computational pipeline for maintaining the repetition rate of output data.
The ADC functioning may be conventionally classified into the following modes: mode of data transformation (normal mode) and mode of calibration. The block of digital correction is used in both modes. Calibration is conducted iteratively from less significant to most significant cascades. For more accurate bias calibration the whole transfer characteristic is divided into segments, corresponding to main code transitions. This makes it possible to calibrate the bias of transfer characteristic at each segment separately, without using averaged value.
This module provides two modes of calibration: calibration of bias and calibration of slope. Debugging mode is also provided for. Debugging mode enables one to indirectly determine the correctness of calibration process and to compute values of coefficients using output module data. When the device is switched into calibration mode, the finite state machine of the digital block emits a signal to output a certain test signal to the input of the cascade being calibrated ; values that are formed at the cascade’s output are compared with the reference ones, and computing of correction coefficients for the corresponding cascade with the subsequent array filling are carried out. This procedure is performed for each cascade only once. Calculations of correction coefficients for 1.5-bit cascade are performed by formula (1). D0–D5 designate data that arrive at the input of 1.5-bit cascade; from these data correction coefficients are subtracted, as well as coefficients computed at the previous stages. K0–K5 designate correction coefficients for 1.5-bit cascade.
Computing procedure for other cascades is carried out similarly — the number of coefficients increases. All arithmetic units are single-type parameterized digital processors designed for signal processing.
Next, in rated operating mode digital correction is carried out with account for value calculated at the stage of calibration using formula (2). That formula is a partial solution for 1.5-bit cascade.
Digital correction of values using formula similar to (2) is carried out for each of cascades being calibrated. Fig. 4 presents the sequence of actions performed in the course of computations.
The first implementation of digital correction algorithm for ADC enabled one to correct five least significant digits of each cascade for rectification of bias error of operational amplifier to 10mW and errors of spread from capacitor nominal to 1 %. With increase in most significant digits, the significance of bits correction decreases: for 1.5-bit cascade the correction constitutes 24mW, and for 3.5-bit cascade — 0.18mW. All computing within calibration block and coefficients of correction has been carried out using floating point numbers. Converters, converting integer values into numbers with floating point and vice versa, have been placed before and after digital correction block respectively. That made it possible to maintain a high accuracy of calculation, including the accuracy of division operations (t5 at Fig. 4). A set of testing chips was issued and respective tests were performed. Actual tests have demonstrated that correlation of five least significant digits is not sufficient. The resulting digital correction block occupied a larger area on a chip and required increased time of calibration at operating frequency.
Aiming to make amendments to the correction algorithm and to optimize the block, i.e. to reduce power consumption and occupied area, the second version of converter has been developed.
The new algorithm performs a quarter of conversion region correction for each cascade: for 1.5-bit cascade — 7bit, for 3.5-bit cascade — 12bit. Besides, blocks without floating point were used, and division operation was substituted by lookup table. Basing on conversion range being corrected a set of values have been computed and then added into the ROM. For each cascade its own ROM has been created. So, after computations the intermediate result t4 was fed to multiplexer, which selects the corresponding value in the ROM, and thus substitutes the operation of division (t5). Table 1 contains comparative characteristics of ADC with digital correction block using floating point and block with fixed point numbers. The results were obtained after physical synthesis using Cadence Encounter RTL Compiler Software.
Fig. 5 presents the ADC input signal correction using a digital block. A digital block for high performance and high precision ADC, operating with fixed point numbers, has been developed within the scope of this work and then further optimized for the applied technological process. An algorithm of digital correction has been developed with account for capacitor nominals spread and operational amplifier bias.
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