Application of Visual Analytics and TCAD Systems in Quality Management of VLSI Crystal Formation Technological Processes
The quality control problem of VLSI production with submicron sizes of elements is currently one of the most urgent and important production problems, whose solution is a very difficult task. The fact is that the technological process of VLSI production has several hundred separate technological operations, with each operation to some extent influencing the output parameters of the VLSI manufactured. Therefore, it is necessary to control the deviation of process parameters, which is usually realized by measuring the electrophysical parameters of special test structures. However, in a number of cases, the existing set of test structures does not always have the ability to provide complete information about the parameters of the technological process.
In this situation, the existing tool for TCAD simulation can be effectively used not only to predict the electrophysical parameters of VLSI elements, which is used at the design stage of quality, but also allows one to identify the operation of the technological process at which the manufacturing mode failed. On the basis of the received information, it is possible to analyze the feasibility of performing technological influences that would neutralize the consequences of the technological equipment regime failure, thereby improving the quality of VLSI crystal manufacturing.
The quality management of VLSI crystals can be simplified in the form of three subsystems:
• subsystem of quality assurance,
• subsystem of quality control,
• subsystem of quality management.
The quality assurance subsystem can be simplified in the form of a block diagram, shown in Fig. 1.
To ensure the quality of VLSI, it is necessary to use various design tools in a single complex. So, for example, on the basis of technical requirements for output parameters of the circuit with the help of schematic CAD, the requirements for the parameters of individual components (transistors, resistors, capacitors etc.) are established. These parameters are extracted from a set of electrical characteristics according to a given algorithm, depending on the design of the component and the technology of its formation. The connection between the design, technology and electrical characteristics of the VLSI component is established using the system of TCAD simulation. Preliminary structural and parametric identification (the so-called calibration) of the models of technological operations is performed to ensure the specified accuracy of the forecast of quality parameters on the basis of modeling. Then, based on information on the permissible deviations of the research component electrical parameters, it is possible to estimate the coefficients of the effect of technological regimes on the quality parameters with the help of the TCAD simulation system. On the basis of the results obtained, tolerances are determined on the variation of technological regimes and their choice is made.
Using the TCAD simulation, it is possible to estimate the yield of suitable VLSIs in the following way. First, using the Monte Carlo statistical test method, several samples of random process parameter values should be generated, and then an instrument-technological simulation should be performed for all random process values generated. After this, it is necessary to estimate the fraction of samples in which the VLSI functional parameters are recognized as satisfactory. This percentage of samples will reflect the yield of those that are eligible. The accuracy of the obtained estimate will be the higher, the more random samples will be analyzed. On the other hand, with quality assurance, time constraints must also be taken into account, since the time of instrument-technological modeling can reach several hours even on sufficiently powerful computers.
TCAD SIMULATION AS AN ELEMENT OF THE QUALITY CONTROL AND MANAGEMENT SUBSYSTEM
TCAD simulation is not only one of the quality assurance tools, but also allows you to analyze the results of an experiment in the event of technological modes deviation of wafers processing and to estimate the magnitude of the deviation of the regimes. Schematically, the VLSI quality management process in this case is shown in Fig. 2.
The process of the technological operation localization, on which the failure occurred, can be described as follows. First, on the basis of TCAD simulation, the relationships between quality parameters and technological modes of performing operations are revealed. These results can be formalized, in particular, in the form of a causal diagram (Ishikawa diagram) . Based on the results of measurements and the above diagram, a hypothesis is advanced about the causes of possible changes in the technological process parameters. In a number of cases, the hypotheses should be such that the existing procedure for attesting equipment does not allow one to see failures in its operation (this technique is also called sabotage analysis). Then, with the help of the same system of TCAD simulation, the consistency of the formulated hypothesis is checked and a proposal is made to improve the process of equipment attestation or to develop additional test structures for monitoring the parameters of the technological process.
In the case of process parameters deviation, it is possible to assess the possibility of wafer restoring to be manufactured on the basis of the TCAD model, namely, to show what wafer treatment and with which regimes should be performed in order to ensure that the quality parameters fall within the tolerance limits established by the technical specification.
In addition, the tool of TCAD simulation allows one to design control and measuring structures of a parametric monitor. So in work  on the basis of the TCAD model the results of test structure designing for control of the LDD-regions doping level are presented. Below it will be described how such a structure allowed one to analyze the fit and rejected wafers and to localize the cause of the reject.
CONTROL AND QUALITY MANAGEMENT OF VLSI ELEMENTS TECHNOLOGICAL PROCESSES USING THE SYSTEMS TCAD SIMULATION ON THE EXAMPLE OF THE ION IMPLANTATION EQUIPMENT FAILURE DETECTION
One of the possible examples of TCAD simulation system application in the control and quality managemant for the produced wafers was the detection of a malfunction in the operation of the implanter. The fact is that according to the results of the operational control it was established that in one of the wafers batches the threshold voltage of the field-effect transistor was significantly overestimated in relation to such a parameter on the wafers of other batches. The analysis of possible reasons for this increase in the threshold voltage made it possible to single out the following possible factors:
1. The thickness of the gate oxide increased,
2. In the gate oxide, the ratio of the charges introduced in the technological process changed,
3. Well or LDD areas doping changed.
The causal diagram of technological parameters influence on threshold voltage is represented on Fig. 3.
The first factor was tested basing on the analysis of the MOS capacitor volt-farad characteristics, which is one of the test elements of a parametric monitor. The result of the test was negative. That is, the thickness of the gate oxide did not change significantly.
The second factor was verified by the wafer annealing, during which all charges in the oxide had to be recombined and, as a consequence, the threshold voltage of the field-effect transistor should be normalized. However, the conducted annealing did not yield any tangible results.
In addition to the measured threshold voltage of the main transistor, an analogous parasitic “bottom” transistor parameter was measured, whose value turned out to be of the order of 20V, which was much less than the calculated TCAD simulation.
The results obtained made it possible to propose a hypothesis that in the well of the field-effect transistor the ratio between the surface and bottom dopant concentrations changed.
To explain this hypothesis, TCAD simulation of the entire VLSI production technological cycle was performed, which showed that this is possible only if the energy of the deep doping well process for the field-effect transistor by the ion implantation method decreases by a factor of 3 (due to the possible loss of charge by three-charged ions of the doping impurity and their further acceleration, but already up to energy 3 times lower than the preset implant).
It should be noted that the standard process of the implanter attestation based on corresponding test structure surface resistance measurements did not show a malfunction in the plant operation, since the surface resistance mainly depends not on the energy but on the doping dose (see Fig. 4), which remained unchanged.
The proposed hypothesis prompted further implanter’s operation quality testing, which revealed the presence of an increased residual pressure in its working zone, which indicated the presence of gas atoms there, which for some reason could not be disposed of and whose presence could lead to the loss of a part of the charge by triply charged ions doping impurity of phosphorus.
For the final verification of hypothesis discussed, experimental wafer samples doped with triply charged phosphorus ions were prepared, after which these samples were sent for SIMS analysis, the results of which are shown in Fig. 5.
It can be seen from the figure that a threefold decrease in the energy of the doping ions actually occurred. The obtained results allowed one to supplement the process of the implanter attestation, including SIMS analysis as an obligatory element of certification.
ANALYSIS OF FIT AND REJECTED WAFERS USING THE PARAMETER CONTROL OPERATION OF LDD-AREAS
In the previous section we talked about the operation of field-effect transistors doping well, whose control was carried out using resistive structures and MOS capacitor structures. However, at that time, control over the LDD regions doping, which were formed by doping with low-energy (5–30keV) single-charged ions of boron (for p-channel transistors) or phosphorus (for n-channel transistors) had not yet been introduced, since the loss of charge by ions in this technological operation was considered unlikely. However, research has shown that the presence of even a small residual resist or oxide layer (of the order about 100–200Å) can disrupt the functioning of the transistor structure . It should be emphasized that controlling the dose of doping in the formation of LDD-regions based on measuring the resistance of the test structures was hampered by the fact that the LDD regions were not present in the “pure form” in the test structures: consequentially with an area of doping wells (having greater resistance), or in parallel with a heavily doped source / drain region (having a lower resistance). Therefore, a special six-contact structure for controlling the resistance of LDD regions was developed, whose description is given in . It should be noted again that, as demonstrated by instrumentation and technology, the quality of LDD regions doping is extremely sensitive to the thicknesses of residual resist and oxide layers.
The developed structure made it possible to establish the cause of the reject in one of the wafer parties, in which the threshold voltages of the field-effect transistors turned out to be approximately 2 times higher than the established norm. At the same time, the control structures of the well doping and heavily doped regions did not have significant deviations in the resistance value relative to the average values by different parties. The measured thickness of the gate oxide also did not differ from the set norm. A significant deviation from the given norm was revealed only when measuring the resistance of LDD regions. Figures 6–7 show the current-voltage characteristics of resistors based on the n- and p-type doping regions for suitable wafers, and in Figures 8–9 show similar characteristics in a batch of defective wafers.
As can be seen from the figures above, resistors formed from LDD regions in a faulty wafer batch have a qualitatively different volt-ampere characteristic in comparison with similar resistors from a suitable wafer batch. Therefore, in accordance with the cause-effect diagram, it is possible to localize the reason for the double increase in the threshold voltage as a malfunction in the LDD-alloying operation, caused either by the presence of impurities on the wafer, or by the presence of residual oxide / resist layers. Therefore, before forming the LDD-areas, it is necessary to visually check the surface of the plates for the presence of resist or oxide residual layers, as well as contaminants. In addition, before forming the protective oxide, it is necessary to check the cleanliness of the wafer surface, as well as constantly to monitor its thickness.
CONCLUSIONS AND RECOMMENDATIONS
TCAD simulation can be an integral tool for both ensuring and controlling and managing the quality of technological processes. With its help, a causal diagram can be developed and an estimate of the technological regimes yield suitable for a given spread can be made.
In addition, this tool allows you to quickly test hypotheses of possible reject causes, conduct sabotage analysis in order to improve the quality of manufactured microcircuits and analyze bottlenecks in the developed technological route of their production.
The tool of TCAD simulation is also an integral aid for the development of test control structures, which was demonstrated when developing a control structure for LDD regions doping.
Thus, the article offers a set of techniques that allow one to ensure the quality management of VLSI production processes.
The authors are grateful to engineer-technologist of the SRISA RAS, O. I. Viletalina for the results of SIMS analysis.
TCAD simulation was carried out in TCAD Sentaurus system, installed on the BMSTU server.
The work was carried out with partial financial support of RFBR (Grant 15-07-03116).
1. Gludkin O. P., Gorbunov N. M. and others. Total Quality Management. Textbook For High Schools / Edited by O. P. Gludkin. — M.: Gorachaya Liniya — Telecom, 2001. — 600 pp. (In Russian).
2. Yashin G. А. [and others] / Yashin G. А., Amirkhanov A. V., Glushko А. А., Zin¬chenko L. А., Makarchuk V. V., Mikhaltsov Е. P. Simulation Of The Process Of Forming LDD-Regions In Submicron SOI MOSFETs In TCAD System. — Nanoindustry. 2017. № S4 (74). P. 218–223.