3D Microassembly Based on Silicon Interconnection Boards and Unpackaged MEMS Elements
Embedded component and 3D microassembly technologies based on silicon interconnection boards  are promising solutions making possible manufacturing of competitive items of microsystem engineering.
3D microassembly includes various methods combinations and design and technology solutions (Fig. 1):
• flip-chip mounting;
• wafer level packaging (WLP);
• TSV (through silicon via), interposers, embedded dies.
3D TSV assembly provides high-density integration as compared with other technologies . TSV is used for 3D assembly of memory microcircuits, MEMS structures together with chips of control logic as well as interposers. However TSV application in microcircuits is restricted by high cost and complexity of technology (Fig. 2).
Basing on design and technological solutions and methods used in flip-chip assembly, 3D IC modules, SiP technology, a new technology of 3D microassemlies using silicon interposers has been developed.
3D microassembly is a system-in-chip and could contain different IC (including NVM, MEMS, RF analog) connected with a silicon interposer providing IC interconnection (Fig. 3а). Chip (unpackaged one) with pre-formed solder bumps on contact pads is mounted on interconnection board using flip-chip method (Fig. 3b). Assembly levels are interconnected by silicon interconnection frames (Fig. 3c), with TSV interconnection and bumps along perimeter for assuring volumetric commutation. Free space in microassembly is filled with two types of compounds (with silicon-organic and epoxy base). Unification is attained by means of equal number of external contact pads (CP) with through-silicon vias for each standard size of interconnection board and frame, with internal topology changing depending on the level scheme. Each level in 3D microassembly may be functionally completed module.
To choose optimal basic material for 3D microassembly interconnection boards, a comparative analysis of most common materials was made (Table 1): Al2O3 — oxide ceramics, AlN — aluminum nitride ceramic, Si — silicon, FR4 — glass-fibre plastic, TGV — hard glass, TQV — synthetic quartz, PTFE/E-glass — material based on polytetrafluorethylene and alumina-borosilicate glass with alkali metals oxides content.
According to the analysis results silicon was selected as material for 3D microassemblies. The application of silicon as interconnection boards makes it possible to provide high heat conduction (50 times greater than in case of LTCC ceramics), higher topological norms than in case of glass-fibre plastic and ceramics (diameter of through vias is less than 70 microns, conductor width and gap between conductors are less than 80 microns), thermal coefficient of linear expansion maximally close to those of basic materials of MEMS elements and integrated circuits.
The advantages of silicon application determine the advantages and disadvantages of TSV technology.
The advantages of TSV are as follows:
• monocrystalline structure of material;
• small diameter and pitch of holes at high aspect ratio;
• availability of material (standard silicon wafers without specified requirements);
• ability to use standard IC manufacturing technologies for layout formation on substrate surface;
• minimal topological norms;
• absence of difference in thermal coefficient of linear expansion between chip material and substrate material with TSV;
• ability to use IC chip as a substrate for TSV;
The disadvantages of TSV are as follows:
• silicon is a semiconductor and has small resistance, so for holes formation in silicon it is necessary to pre-form a layer of dielectric, as a rule, oxide or nitride of silicon;
• silicon is relatively brittle material;
• expensive technology of TSV formation within IC structure with subsequent 3D assembly.
For vertical level interconnection it is necessary to provide plated-through holes with high conductance in interconnection silicon boards (Fig. 4). The formation of through holes in silicon with maximally low resistance is a most complex task and a real challenge facing domestic microelectronics.
INVESTIGATION OF PLATED-THROUGH HOLES FORMATION IN SILICON
Firstly, resistance of metals deposited on the holes surface was simulated. It was done under following conditions: the ground plane and the source plane were located on wafer’s contact pads at maximum distance between upper and lower sides (the source plane at the edge of upper contact pad, the ground plane at the opposite side relative to the source plane edge of the lower contact pad), the main conducting material being copper. To simplify calculations the current source was set equal to 1А (Fig. 5). Contact pads dimensions from both sides of the carrier make 0.8 × 0.4mm. Silicon wafer thickness is 300 microns, SiO2 thickness is 1 micron, thickness of chrome sublayer is 50nm.
According to the results of resistance simulation, the dependence of plated-through hole resistance on plating thickness has been determined:
1. For 10 micron thick metal layer the resistance is: R10 = 1.7 mOhm;
2. For 15 micron thick metal layer the resistance is: R15 = 1.3 mOhm;
3. For ∅60 micron hole completely filled with metal: R30 = 0.7 mOhm.
In the research we used monocrystalline silicon with p-type conductance, with electrical resistivity ranging in value from 0.5 to 20 Ohm∙cm, with “111” orientation and 300 microns thick; diameters of formed holes were ranging in value from 40 to 120 microns.
Holes different in diameter were formed at deep plasma etching installation. Both through holes and blind holes were etched depending on the selected technological process. The holes shape effect on peculiarities of subsequent metallization process has been determined. Holes in silicon were formed by means of Bosсh-process. Parameters of Bosh-process vary depending on selected design and technological variant of holes formation. An additional stage of isotropic etching was introduced for bevels formation. Fig. 6 presents examples of different variants of holes profile in silicon wafer. The tests were carried out using electron microscope FEI Quanta 3D FEG.
From all tested methods of through holes formation in silicon wafer we have chosen the one with vertical walls and small bevels at both sides of the hole. According to the results of the tests it was determined that preferable variant of through holes metallization technology is a route providing pre-coating by chrome and copper by means of magnetron method with subsequent copperplating using process of electrochemical deposition. Fig. 7 presents images of holes metallization after sublayer formation and electrochemical deposition of copper (holes profiles for tests were obtained using sawing wafer technique at predefined depth with subsequent cracking). In case of magnetron sputtering the deposited layer has characteristic columnar structure described by Movchan-Demchishin model. The copper layer morphology significantly depends on deposition rate, and there exists a possibility of obtaining porous and compact non-porous layers . While developing the electrochemical deposition process different modes were selected so as to provide maximal dense non-porous structure of deposited film.
Using the results of tests conducted for technological processes of holes formation, dielectric layer deposition and metallization, optimal modes were selected and technology of interposers manufacturing was developed (Fig. 8), as well as resistance measurements in via holes in manufactured test samples were conducted (Fig. 9).
The mean resistance value made 23.5mOhm (the result was obtained with due account of resistance at places of CP and measuring probes contact). Measurements were made using Agilent 34405A multimeter.
Two experiments were conducted to determine samples operability for extreme values of operating temperatures and vibration impact.
The mean resistance value of via holes after thermal effect allowing for an error makes 24.1mOhm. Test conditions were as follows: decrease in temperature from room temperature to –60 °С in an hour, and then gradual heating up to +85 °С in two hours and cooling down to room temperature in an hour.
The mean resistance value of via holes after random vibrations in the range 20–2000Hz allowing for an error makes 23.8mOhm. Test conditions were as follows: gradual frequency increase from 20 to 2000Hz with acceleration amplitude being 5g.
The experimental data make it possible to conclude that the quality of metallization in test samples holes is sufficient.
SAMPLES OF INTERPOSERS AND 3D MICROASSEMBLIES
Basing on the results obtained, samples of interconnection boards and frames were manufactured (Fig. 10) with plated-through holes in silicon (TSV) wafer having the following parameters:
• planar dimensions: 15 × 15mm;
• thickness: 335±10 microns;
• number of interconnection layers: 2;
• diameter of plated-through holes: 60 microns;
• main material for via holes filling: Cu;
• layout norms of conductor thickness/gap: 0.09/0.09mm.
Interconnection board is the layer base and main element used for 3D microassembly. Each layer contains unpackaged microcircuit prototype responsible for the defined functional. Microcircuit die is mounted on interposer using flip-chip technology with the help of solder bumps made of SAC305 alloy (Sn = 96.5 %; Ag = 3 %; Cu = 0.5 %) with initial diameter 100 microns (Figs 11а, 11b, 11c). It is possible to use both lead-free bumps and materials with Au or solders containing lead with various diameters. The gap between die and interconnection board surface is filled with superfluid compound (Fig. 11d). The layer structure contains a silicon frame necessary to perform vertical interconnections with other microassembly layers. The frame is mounted on the layer base using flip-chip technology. The thickness of the frame with bumps is just over the thickness of the die mounted on bumps and contains exactly the same number of external contact pads with TSV-holes as the number of contact pads on interconnection board.
Upon mounting interconnection frame the layer is filled with heat conducting compound. The other layers are manufactured similarly and sequentially mounted at the first level to obtain 3D microassembly (Fig. 12а, 12b).
Basing on obtained results 3D microassembly of accelerometers has been developed with unpackaged MEMS and signal processing microcircuits on silicon interconnection boards.
Microassebly includes two levels:
1st level: two “encapsulated” sensitive elements of MEMS accelerometers with passive components mounted on interposer and silicon frame with plated-through holes and bumps.
The encapsulated technology involves the creation of a protective cover above inertial mass of sensitive MEMS element. The mobility of inertial structure elements is provided by a dimple in the silicon cover connected with the upper part of sensitive element by means of splicing technique. To provide electrical contact with sensitive element plated-though TSV holes are formed in the cover (Fig. 13).
2nd level: chip of microcircuit for signals processing with passive components mounted on interposer and a silicon frame with plated-through holes and bumps (Fig. 14).
Parameters of model for 3D microassembly of accelerometer are as follows:
• planar dimensions: 15 × 15mm
• height: ~ 1.5mm;
• number of external CP: 48 pc.;
• diameter of through holes in frame: 0.1mm;
• measurement range: ±1…±200g;
• non-linearity: up to 0.2 %;
• noise spectral density: up to 10 — 5g/Hz−1/2;
• range of operating temperatures: from — 60 up to +125 °С.
Key peculiarities of 3D microassembly are integration of heterogeneous domestic elements (MEMS, IC) into a single, functionally completed system with maximally dense placement, the use of silicon as interconnection board, vertical interconnection of microassembly levels with application of TSV and bumps, application of “encapsulated” MEMS, absence of wired joints for microassembling elements on interposer.
The research has made it possible to obtain the following results:
1. Main processes of plated-through holes formation in silicon interconnection boards have been developed;
2. Tests of TSV holes from 40 to 120 micron in diameter made in silicon wafer with p-type conductance and resistance ranging in value from 0.5 to 20Ohm∙cm with “111” orientation and 300 micron thickness have been carried out;
3. Samples of silicon interconnection boards have been manufactured (interposers) with the planar dimensions 15 × 15mm, thickness ~ 330 microns, with TSV holes 60 microns in diameter, with mean value of via holes resistance 23mOhms (the main conducting material being copper);
4. 3D microassembly technology has been developed and main stages of its manufacturing have been worked out: bumps installation on contact pads, mounting dies on interposer using flip-chip method, levels formation of 3D microassembly, filling under chip gap and layers with compounds, layers assembling and installation;
5. 3D microassembly accelerometer model has been developed basing on silicon interconnection boards and unpackaged MEMS elements and IC.
The lead of 3D microassembly technology presented in this paper has been developed jointly with JSC “NIIME”.
1. Vertyanov D. V., Petrov V. S., Shabu¬nin D. A., Burakov M. M., Brykin A. V. Preimushchestva tekhnologii vnutrennego montazha pri proizvodstve inertsial'nykh sistem na osnove otechestvennykh MEMS. Nauchno-tekhnologicheskii zhurnal “Nanoindustriya. Spetsvypusk 2017 (74)”. — S. 579–580. (In Russian).
2. Garrou P., Bower Ch., Ramm P. Handbook of 3D Integration. Technology and Applications of 3D Integrated Circuits. 2008.
3. Boyko A., Gaev D., Timoshenkov S., Litmanovich D. “Controllable Growth of Copper Fractal Aggregates on Structurally Modified Silicon Surface”, Proc. of the XXXII Int. Sc. Conf. ELNANO’2013, Kyiv, 2013. pp. 185–187.