Wafer level packaging of MEMS prior to wafer dicing can provide protection from particles and dicing slurry, while significantly reducing form factor and the overall die cost.
I ncreasingly, many MEMS devices, such as microsensors, require a vacuum or controlled atmosphere for operation. This could be used to control parameters such as the Q-factor (amount of damping), or to provide a reference vacuum for pressure sensors, or to reduce absorption in infrared sensors and improve sensitivity and resolution. Two such examples of wafer level packaging are silicon capping and thin film encapsulation, each providing benefits for specific packaging applications. SILICON CAPPING One common method of packaging micromachined devices is to bond a silicon cap wafer to the device wafer (Fig.1). This can be used for multiple sensors on the same die, utilizes metal-eutectic bonding and requires less bonding area than traditional glass frit capping. Through silicon vias (TSVs) can be used instead of I/O pads – further reducing form factor size. THIN FILM ENCAPSULATION A lower cost and simpler packaging alternative is thin film encapsulation. By eliminating the need for sealing/bonding and a capping wafer, thin film encapsulation is, for some MEMS designs, the simplest and lowest cost packaging alternative.
The technique uses a double sacrificial layer (normally silicon or silicon oxide) which supports the MEMS structure and defines a space above the structure while a cap layer is deposited over the device layer (Fig.s 2 & 3). Holes in the capping layer allow an etchant (e.g vapor HF or XeF2 depending on the sacrificial material) to remove the sacrificial layer and “release” the moving MEMS structure (Fig.s 4 & 5). These holes must then be closed by depositing a final sealing layer. Typical sealing materials include epi- or LPCVD PolySi , PECVD SiOx or SiNy or metals such as aluminium (Fig.6). EXAMPLES OF WAFER LEVEL PACKAGING OF MEMS USING THIN FILM ENCAPSULATION Ideally, the device package should be sealed without removing the wafer from vacuum, to avoid yield or performance loss from unwanted absorption of contaminating gases or moisture. Different MEMS devices require different cavity pressures, and the required pressure/gas composition can be tailored prior to sealing. Stress, temperature and vacuum requirements will determine optimum sealing material (Fig.s 7 & 8). Why use SPTS? • Market-leading DRIE etch processes (Fig.9) to define MEMS structures and vent holes, with high etch rates, low feature tilt and unique Claritas end-point system; • Low temperature PECVD compatible with temperature-sensitive MEMS devices; • HF or XeF2 vapor etch processes can be integrated onto production-proven cluster systems (Fig.10); • LPCVD batch processing for cost-effective deposition of thick polysilicon layers, and dielectrics where low temperature is not a requirement; • Versalis fxP (Fig.11) enables integration of different processes into a single cluster tool to reduce cost of ownership. ■ For more information about our wafer level packaging solutions, please email firstname.lastname@example.org