rus
Special Issue/2019
A. E. Agafonov, S. I. Boroshko, P. G. Kirichenko, O. V. Sysoeva, I. V. Tarasov, A. G. Khokhlova
A 65-nm videocontroller synthesizer for monitors with resolution up to 4K
A 65-nm videocontroller synthesizer for monitors with resolution up to 4K
The paper highlights the design process of clock synthesizer for videocontroller implementation based on phase-locked loop (PLL) with autoshifting circuit and programmable charge pump (CP). An architecture of synthesizer for interface clock frequency with step 250 kHz and less without delta-sigma modulator, phase interpolator and randomizator in the feedback loop has been proposed.
The paper highlights the design process of clock synthesizer for videocontroller implementation based on phase-locked loop (PLL) with autoshifting circuit and programmable charge pump (CP). An architecture of synthesizer for interface clock frequency with step 250 kHz and less without delta-sigma modulator, phase interpolator and randomizator in the feedback loop has been proposed.
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