rus
Special Issue/2019
N. N. Egorov S. A. Golubkov S. D. Fedotov V. N. Statsenko A. A. Romanov V. A. Metlov
Studying electron mobility and volt-ampere characteristics of fi eld-eff ect transistors depending on structural and electrophysical characteristics of ultrathin silicon on sapphire
Studying electron mobility and volt-ampere characteristics of fi eld-eff ect transistors depending on structural and electrophysical characteristics of ultrathin silicon on sapphire
The paper presents a comparison of crystalline quality between domestic fabricated and imported SOS wafers. The wafers were produced by CVD and improved by solid phase epitaxial regrowth (SPER) process with thinning. The XRD measurement of ultrathin (≤100 nm) SOS 6 inch wafers revealed Si(400) diffraction peaks with FWHM of ~0.27° for domestic and FWHM ~0.30° for imported wafers. RHEED and TEM measurements have shown the absence of micro-twins reflexes and reduction in the defect density by more than 2 orders of magnitude for ultrathin SOS after SPER with Si+ implantation. Besides, it was revealed that the utilization of SPER leads to an increase in electron mobility >50 % as compared to standard CVD SOS wafer. However, the increase in carrier concentration in Si-layer up to ~3.13 · 1012 cm−2 leads to a fall in electron mobility down to ~150–160 cm2/W∙s. Threshold voltage of MOSFETs (n-channel) has shown slight dependence on the level of carrier concentration and varied in the range of 0.25–0.75 W.
The paper presents a comparison of crystalline quality between domestic fabricated and imported SOS wafers. The wafers were produced by CVD and improved by solid phase epitaxial regrowth (SPER) process with thinning. The XRD measurement of ultrathin (≤100 nm) SOS 6 inch wafers revealed Si(400) diffraction peaks with FWHM of ~0.27° for domestic and FWHM ~0.30° for imported wafers. RHEED and TEM measurements have shown the absence of micro-twins reflexes and reduction in the defect density by more than 2 orders of magnitude for ultrathin SOS after SPER with Si+ implantation. Besides, it was revealed that the utilization of SPER leads to an increase in electron mobility >50 % as compared to standard CVD SOS wafer. However, the increase in carrier concentration in Si-layer up to ~3.13 · 1012 cm−2 leads to a fall in electron mobility down to ~150–160 cm2/W∙s. Threshold voltage of MOSFETs (n-channel) has shown slight dependence on the level of carrier concentration and varied in the range of 0.25–0.75 W.
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