rus
Issue #2/2020
S.O.Belostotskaya, A.A.Lykyanov, A.S.Roslyakov, A.N.Semyonov, R.A.Fedorov
Reliability assessment of the one-time programmable read-only memory devices produced on the basis of jumpers programmable with the use of the electromigration mechanism (eFuse)
Reliability assessment of the one-time programmable read-only memory devices produced on the basis of jumpers programmable with the use of the electromigration mechanism (eFuse)
DOI: 10.22184/1993-8578.2020.13.2.114.121
In this work the reliability of the one-time read-only memory devices (OPROM) implemented on the HCMOS8D technology with topological standards of 180 nm and designed to be integrated into the base crystal of the 5521TP series is evaluated. With the use of the base layers of HCMOS8D technology, the structure and design of the programmed by the electromigration mechanism of the elements of the EEPROM – jumpers (eFuse), on the basis of layers of n+-polysilicon and nickel silicide were developed. A technique has been developed to assess the reliability of eFuse intended for use as a part of memory cells in the 5521TP series base crystal. eFuse guarantees the preservation of residual resistance within specified limits throughout the life of the microcircuit.
In this work the reliability of the one-time read-only memory devices (OPROM) implemented on the HCMOS8D technology with topological standards of 180 nm and designed to be integrated into the base crystal of the 5521TP series is evaluated. With the use of the base layers of HCMOS8D technology, the structure and design of the programmed by the electromigration mechanism of the elements of the EEPROM – jumpers (eFuse), on the basis of layers of n+-polysilicon and nickel silicide were developed. A technique has been developed to assess the reliability of eFuse intended for use as a part of memory cells in the 5521TP series base crystal. eFuse guarantees the preservation of residual resistance within specified limits throughout the life of the microcircuit.
Reliability assessment of the one-time programmable read-only memory devices produced on the basis of jumpers programmable with the use of the electromigration mechanism (eFuse)
INTRODUCTION
The use of eFuse jumpers based on metal-polysilicon silicide makes it possible to implement various design options for VLSI in the submicron CMOS technology. An eFuse programmable with the use of the electromigration mechanism is the preferred option when designing complex VLSI function blocks in comparison with laser correction jumpers since programming, in the first case, can be implemented without the participation of the manufacturer. It was previously shown in [1] that it is possible, in principle, to use the complex functional blocks of the OTPZU based on fusible jumpers for their one-time programming in the microcircuits developed on the base crystals (BC) of the 5521TP series.
The eFuse discussed in [2–4] uses the electromigration mechanism to increase the electrical resistance of the jumper. Physical breakdown of the bridge body occurs due to migration of the silicide layer ions from anode to cathode by the electron flow, causing an increase in the bridge resistance by several orders of magnitude [2].
Metals are considered to be less resistant than silicides to the electromigration process [2], but the metal-based eFuse programming current is more than 20 times greater than the eFuse programming current based on silicide-polysilicon [1]. Silicides are also widely used both for the formation of low-resistance contacts to diffusion regions, and for interconnect elements. In works [3, 4] it was shown that it is possible to successfully use the process of electromigration of silicide layers in individual electrically programmed circuit elements. In these studies, layers of cobalt silicide (CoSi2) and tungsten silicide (WSi2) on a heavily doped gate polysilicon layer were used as a silicide layer in eFuse elements.
Reliability assessment in works [3, 4] was carried out in accordance with the standards JESD22-F104, JESD22-F113, JESD22-F108, JESD22-F110 providing tests at elevated temperature, electric displacement, thermal cycling, as well as accelerated stress tests at elevated temperature and humidity.
In this work, the reliability assessment was carried out on test structures that included only single eFuses to minimize the influence of any stray components of the electric circuit. The paper presents: the design and layered structure of a single eFuse; eFuse programming algorithm with the definition of its programming criteria; eFuse research methodology for reliability; and the output criterion ensuring eFuse reliability over the entire VLSI service lifetime.
еFuse Design and Layering
The optical image of a fragment of the 5521TP series microcircuit, which includes the developed single eFuse, their outline design and layered section, is shown in Fig.1. The developed eFuse elements were integrated into the HCMOS8D basic technology with 180 nm design standards based on the base layers without the use of additional technological cycles. The eFuse jumpers present a layer of heavily doped n+ gate polysilicon on an insulating oxide completely coated with a layer of nickel silicide NiSi2. Expansion of the elemental base in the HCMOS8D technology with the developed by us eFuses allowed us to develop both the core memory and analog circuit tuning circuits.
To assess reliability, three eFuse designs were applied with different W/L ratios (Table 1). The number of test samples of each eFuse modification was 20 pieces.
The eFuse programming algorithm with the definition of its programming criterion
The eFuse programming algorithm has been developed based on the limiting parameters of TU AENV.431260.412TU. For programming and operation of eFuse, the supply voltage is the limiting parameter. According to the requirement for electrical parameters and operating modes of the TU AENV.431260.412TU for the 5521TR base crystal, the range of maximum permissible supply voltages of the BK 5521TR varies from 2.7 to 3.63 V, its limit value being 4 V.
To determine the state of eFuse, an extension circuit has been developed that operates in the range of 10 kΩ and higher.
The first and second modifications (see Table 1) of eFuse were programmed under the following conditions: a voltage of 3.63 V for a duration of 100 ms was applied to one eFuse pin with a limit of the maximum current value through eFuse that equals 100 mA, no voltage was applied to the second pin. The third modification of eFuse, when programming at a voltage of 3.63 V, did not satisfy the minimum residual resistance parameter. To obtain statistics on the residual resistance value, the third modification was programmed at a maximum supply voltage of 4 V. The time and current conditions remained the same.
The main output electrophysical parameter characterizing the implementation of the eFuse programming process was a change in the initial resistance of the jumper body by at least 2 orders of magnitude. The scatter of the residual resistance values of the three eFuse modifications under study before and after the programming process is shown in Table 2.
The data obtained show that eFuse of modification 1 has the largest programming current out of three modifications for which a large programming transistor will be needed in future, which will subsequently affect the area occupied by the memory cell based on this eFuse variant. Modification 1 is programmed with the maximum permissible supply voltage. After programming, this eFuse modification has the largest resistance spread out of all presented, as well as the largest change in residual resistance during testing. The results of resistance changes during eFuse operation are presented below in Fig.3.
The programming voltage of the second modification eFuse is the same as the programming voltage of the first modification, but the eFuse of the second modification has a lower programming current, a smaller spread of resistances after programming and a smaller spread of residual resistance during operation. The results of resistance changes during eFuse operation are presented below in Fig.4.
Modification 3 provides for the minimum programming current from the studied modifications but the voltage required for programming does not fall within the maximum permissible supply voltage range for the 5521TP base crystal.
Based on the obtained data, we can conclude that the second modification of eFuse is the best one out of the presented modifications.
Methods of research on reliability
Chips of the 5521TP series must be resistant to special factors with characteristics 7.I, 7.C and 7.K in accordance with GOST RV 20.39.414.2. One of the main criteria for the quality of a microcircuit is its reliability over the entire service life. To confirm the reliability of the developed eFuse cell, a methodology was developed for assessing the reliability of this unit in accordance with GOST RV 20.39.414.2.
The eFuse reliability assessment methodology was aimed at studying the thermal stability of eFuse resistance, including stress, relaxation, and related changes in residual resistance. The microcircuit was exposed to elevated temperature (125 °С) at a switching frequency of the supply voltage from 0.05 Hz to 60 Hz.
The block diagram developed for the eFuse test is shown in Fig.2.
For reliability testing, the chip with eFuse was installed in accordance with the circuit shown in Fig.2. The tests were carried out at a temperature of 125 °C at a supply voltage of 3.6 V ± 5%.
The eFuse research algorithm consistently included the measurement of eFuse resistance before programming, the eFuse programming, the measurement of resistance after programming, and testing of the chip for 3,000 hours with an intermediate monitoring of the eFuse residual resistance through 48, 500, 1,000, 1,500, 2,000, 2,500 and 3,000 hours.
An output criterion that ensures eFuse reliability over the entire VLSI service lifetime
The main performance criteria for a single eFuse are the residual resistance and the range of variation of the residual resistance. Changing the residual resistance over time under the influence of external factors can affect the correct performance of the chip. To check the residual resistance, tests were carried out, eFuses with geometrical sizes of 0.5 / 0.18 μm and 1.0 / 0.18 μm were selected, since the eFuse data is programmed using the maximum allowable supply voltage. The paper presents the results of a study of changes in residual resistance developed by eFuse. The range of changes in residual resistance over time has been identified. The results are presented in Figs.3, 4.
Fig.3 shows the time dependence of the residual resistance of three identical eFuse of the first modification. This figure shows the range of changes in residual resistance over time.
The range of the residual resistance variation in eFuse with geometric dimensions L / W = 0.5 / 0.18 μm is from 10 kΩ to 1 GΩ.
Fig.4 shows the dependence of the residual resistance of three identical eFuse of the second modification on the test time. This figure shows the range of change in residual resistance over time.
The range of variation of the residual resistance eFuse with geometric dimensions L / W = 1.0 / 0.18 μm is from 10 MΩ to 10 GΩ.
DISCUSSION
From the data presented in the work we can conclude that not all developed eFuse geometries can be used in the cells of the RAM. The cell layout of the RAM based on the developed eFuse is presented in Fig.5. eFuse with geometric dimensions of 0.5 / 0.18 μm has a large spread of residual resistance after programming (from 500 kΩ to 400 MΩ), as well as a large spread of residual resistance during the test (from 10 kΩ to 100 MΩ). This eFuse modification needs an additional definition circuit that can track resistance changes in the range of 10 kΩ to 10 MΩ.
The developed eFuse modification with geometric dimensions of 1.0 / 0.18 μm has a stable large residual resistance after programming (from 300 MΩ to 500 MΩ). The residual resistance during the test varies in the range from 45 MΩ to 8 GΩ, which makes it possible to weaken the requirements for the additional determination circuit. The memory cell based on this eFuse has a large area and needs a larger transistor for programming, the memory cell diagram is shown in Fig.2.
The modification with geometric dimensions of 1.7 / 0.18 microns is not suitable for further use in the developed memory cells since the programming voltage exceeds the maximum voltage for the developed 5521TP series crystal.
The wiring diagram for eFuse programming as part of the EEPROM is shown in Fig.5.
CONCLUSIONS
In this paper we presented three modifications of the eFuse jumpers developed on the basis of the base layers of the HCMOS8D technology, described the programming mode and selected a criterion for evaluating reliability. Of all those presented eFuses only the second modification satisfies the reliability criterion. This modification has a stable large (above 1 MΩ) residual resistance after programming as well as during the test. The carried out tests confirm the reliability of the developed design during the entire service life of the microcircuit declared in TU AENV.431260.412. The developed eFuse modification can later be used as a part of the unit of a one-time programmable read-only memory device as a part of the base crystal of the 5521TP series. ■
INTRODUCTION
The use of eFuse jumpers based on metal-polysilicon silicide makes it possible to implement various design options for VLSI in the submicron CMOS technology. An eFuse programmable with the use of the electromigration mechanism is the preferred option when designing complex VLSI function blocks in comparison with laser correction jumpers since programming, in the first case, can be implemented without the participation of the manufacturer. It was previously shown in [1] that it is possible, in principle, to use the complex functional blocks of the OTPZU based on fusible jumpers for their one-time programming in the microcircuits developed on the base crystals (BC) of the 5521TP series.
The eFuse discussed in [2–4] uses the electromigration mechanism to increase the electrical resistance of the jumper. Physical breakdown of the bridge body occurs due to migration of the silicide layer ions from anode to cathode by the electron flow, causing an increase in the bridge resistance by several orders of magnitude [2].
Metals are considered to be less resistant than silicides to the electromigration process [2], but the metal-based eFuse programming current is more than 20 times greater than the eFuse programming current based on silicide-polysilicon [1]. Silicides are also widely used both for the formation of low-resistance contacts to diffusion regions, and for interconnect elements. In works [3, 4] it was shown that it is possible to successfully use the process of electromigration of silicide layers in individual electrically programmed circuit elements. In these studies, layers of cobalt silicide (CoSi2) and tungsten silicide (WSi2) on a heavily doped gate polysilicon layer were used as a silicide layer in eFuse elements.
Reliability assessment in works [3, 4] was carried out in accordance with the standards JESD22-F104, JESD22-F113, JESD22-F108, JESD22-F110 providing tests at elevated temperature, electric displacement, thermal cycling, as well as accelerated stress tests at elevated temperature and humidity.
In this work, the reliability assessment was carried out on test structures that included only single eFuses to minimize the influence of any stray components of the electric circuit. The paper presents: the design and layered structure of a single eFuse; eFuse programming algorithm with the definition of its programming criteria; eFuse research methodology for reliability; and the output criterion ensuring eFuse reliability over the entire VLSI service lifetime.
еFuse Design and Layering
The optical image of a fragment of the 5521TP series microcircuit, which includes the developed single eFuse, their outline design and layered section, is shown in Fig.1. The developed eFuse elements were integrated into the HCMOS8D basic technology with 180 nm design standards based on the base layers without the use of additional technological cycles. The eFuse jumpers present a layer of heavily doped n+ gate polysilicon on an insulating oxide completely coated with a layer of nickel silicide NiSi2. Expansion of the elemental base in the HCMOS8D technology with the developed by us eFuses allowed us to develop both the core memory and analog circuit tuning circuits.
To assess reliability, three eFuse designs were applied with different W/L ratios (Table 1). The number of test samples of each eFuse modification was 20 pieces.
The eFuse programming algorithm with the definition of its programming criterion
The eFuse programming algorithm has been developed based on the limiting parameters of TU AENV.431260.412TU. For programming and operation of eFuse, the supply voltage is the limiting parameter. According to the requirement for electrical parameters and operating modes of the TU AENV.431260.412TU for the 5521TR base crystal, the range of maximum permissible supply voltages of the BK 5521TR varies from 2.7 to 3.63 V, its limit value being 4 V.
To determine the state of eFuse, an extension circuit has been developed that operates in the range of 10 kΩ and higher.
The first and second modifications (see Table 1) of eFuse were programmed under the following conditions: a voltage of 3.63 V for a duration of 100 ms was applied to one eFuse pin with a limit of the maximum current value through eFuse that equals 100 mA, no voltage was applied to the second pin. The third modification of eFuse, when programming at a voltage of 3.63 V, did not satisfy the minimum residual resistance parameter. To obtain statistics on the residual resistance value, the third modification was programmed at a maximum supply voltage of 4 V. The time and current conditions remained the same.
The main output electrophysical parameter characterizing the implementation of the eFuse programming process was a change in the initial resistance of the jumper body by at least 2 orders of magnitude. The scatter of the residual resistance values of the three eFuse modifications under study before and after the programming process is shown in Table 2.
The data obtained show that eFuse of modification 1 has the largest programming current out of three modifications for which a large programming transistor will be needed in future, which will subsequently affect the area occupied by the memory cell based on this eFuse variant. Modification 1 is programmed with the maximum permissible supply voltage. After programming, this eFuse modification has the largest resistance spread out of all presented, as well as the largest change in residual resistance during testing. The results of resistance changes during eFuse operation are presented below in Fig.3.
The programming voltage of the second modification eFuse is the same as the programming voltage of the first modification, but the eFuse of the second modification has a lower programming current, a smaller spread of resistances after programming and a smaller spread of residual resistance during operation. The results of resistance changes during eFuse operation are presented below in Fig.4.
Modification 3 provides for the minimum programming current from the studied modifications but the voltage required for programming does not fall within the maximum permissible supply voltage range for the 5521TP base crystal.
Based on the obtained data, we can conclude that the second modification of eFuse is the best one out of the presented modifications.
Methods of research on reliability
Chips of the 5521TP series must be resistant to special factors with characteristics 7.I, 7.C and 7.K in accordance with GOST RV 20.39.414.2. One of the main criteria for the quality of a microcircuit is its reliability over the entire service life. To confirm the reliability of the developed eFuse cell, a methodology was developed for assessing the reliability of this unit in accordance with GOST RV 20.39.414.2.
The eFuse reliability assessment methodology was aimed at studying the thermal stability of eFuse resistance, including stress, relaxation, and related changes in residual resistance. The microcircuit was exposed to elevated temperature (125 °С) at a switching frequency of the supply voltage from 0.05 Hz to 60 Hz.
The block diagram developed for the eFuse test is shown in Fig.2.
For reliability testing, the chip with eFuse was installed in accordance with the circuit shown in Fig.2. The tests were carried out at a temperature of 125 °C at a supply voltage of 3.6 V ± 5%.
The eFuse research algorithm consistently included the measurement of eFuse resistance before programming, the eFuse programming, the measurement of resistance after programming, and testing of the chip for 3,000 hours with an intermediate monitoring of the eFuse residual resistance through 48, 500, 1,000, 1,500, 2,000, 2,500 and 3,000 hours.
An output criterion that ensures eFuse reliability over the entire VLSI service lifetime
The main performance criteria for a single eFuse are the residual resistance and the range of variation of the residual resistance. Changing the residual resistance over time under the influence of external factors can affect the correct performance of the chip. To check the residual resistance, tests were carried out, eFuses with geometrical sizes of 0.5 / 0.18 μm and 1.0 / 0.18 μm were selected, since the eFuse data is programmed using the maximum allowable supply voltage. The paper presents the results of a study of changes in residual resistance developed by eFuse. The range of changes in residual resistance over time has been identified. The results are presented in Figs.3, 4.
Fig.3 shows the time dependence of the residual resistance of three identical eFuse of the first modification. This figure shows the range of changes in residual resistance over time.
The range of the residual resistance variation in eFuse with geometric dimensions L / W = 0.5 / 0.18 μm is from 10 kΩ to 1 GΩ.
Fig.4 shows the dependence of the residual resistance of three identical eFuse of the second modification on the test time. This figure shows the range of change in residual resistance over time.
The range of variation of the residual resistance eFuse with geometric dimensions L / W = 1.0 / 0.18 μm is from 10 MΩ to 10 GΩ.
DISCUSSION
From the data presented in the work we can conclude that not all developed eFuse geometries can be used in the cells of the RAM. The cell layout of the RAM based on the developed eFuse is presented in Fig.5. eFuse with geometric dimensions of 0.5 / 0.18 μm has a large spread of residual resistance after programming (from 500 kΩ to 400 MΩ), as well as a large spread of residual resistance during the test (from 10 kΩ to 100 MΩ). This eFuse modification needs an additional definition circuit that can track resistance changes in the range of 10 kΩ to 10 MΩ.
The developed eFuse modification with geometric dimensions of 1.0 / 0.18 μm has a stable large residual resistance after programming (from 300 MΩ to 500 MΩ). The residual resistance during the test varies in the range from 45 MΩ to 8 GΩ, which makes it possible to weaken the requirements for the additional determination circuit. The memory cell based on this eFuse has a large area and needs a larger transistor for programming, the memory cell diagram is shown in Fig.2.
The modification with geometric dimensions of 1.7 / 0.18 microns is not suitable for further use in the developed memory cells since the programming voltage exceeds the maximum voltage for the developed 5521TP series crystal.
The wiring diagram for eFuse programming as part of the EEPROM is shown in Fig.5.
CONCLUSIONS
In this paper we presented three modifications of the eFuse jumpers developed on the basis of the base layers of the HCMOS8D technology, described the programming mode and selected a criterion for evaluating reliability. Of all those presented eFuses only the second modification satisfies the reliability criterion. This modification has a stable large (above 1 MΩ) residual resistance after programming as well as during the test. The carried out tests confirm the reliability of the developed design during the entire service life of the microcircuit declared in TU AENV.431260.412. The developed eFuse modification can later be used as a part of the unit of a one-time programmable read-only memory device as a part of the base crystal of the 5521TP series. ■
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