Currently, with the development of high-speed systems of information processing, a modern domestic electronic component base, which includes both digital and analog IP cores, including the frequency synthesizers, becomes in demand [1, 2]. The output frequencies of the synthesizers in such devices can range from tens of MHz to several GHz. Such Russian companies as Module V, Mikron, ELVEES, etc. develop IP cores of frequency synthesizers based on phase-locked loop (PLL) for system-on-chip. SMC "Technological Centre" develops radiation-resistant specialized VLSI IC based on gate arrays of 5521 family. Due to structural and technological features of this gate arrays family, the use of IP cores of frequency synthesizers of third-party companies in a ready kind is difficult. So there is a need for the development of IP core of frequency synthesizer especially for 5521 gate array family [3, 4]. Direct and indirect (active) synthesis are the most frequently used methods of frequency synthesis. In the first case the output frequency is generated by operations of mixing, multiplication/division, filtering the reference clock signals, in the second case the indirect synthesis is carried out, when the output frequency is formed without non-linear transformations by using the tunable oscillator. The main advantages of direct methods are the high speed and small step of frequency tuning. The advantages of indirect methods are a low level of side spectral components and easier implementation compared to direct synthesis.
In the developed frequency synthesizer (FS) the classical PLL circuit is used. From the diversity of the systems based on PLL, a single-loop pulse structure with a single tunable oscillator was chosen. A generic block diagram of the FS is shown in Fig.1. The structure of the frequency synthesizer includes: external reference generator (RG); fixed-division-ratio prescaler (FDRP); phase-frequency detector (PFD); charge pump (CP); passive low-frequency filter (LFF); voltagecontrolled oscillator (VCO); divider with a variable division ratio in feedback loop (DVDR). RG is a source of reference frequency f0 and is based on an external temperature-compensated crystal oscillator. The stability of the output frequency (fвых) of frequency synthesizer is largely determined by the stability of the frequency f0. The main purpose of the prescaler is the determination of the permissible frequency range of the reference oscillator. For the described IP core, f0 can take values from 4 to 6 MHz. FDRP receives frequency f0 from the RG and divides it by a fixed coefficient "4" (f1 = f0/4), that is, the frequency f1 from the output of the prescaler takes the values from 1 to 1.5 MHz. In case of an alternative version of the f0 frequency range from 1 to 1.5 MHz, the prescaler is not used. PFD is a digital discriminator. To one input of PFD the signal of frequency f1 is given and to the second input – of frequency fд. Information about mismatch in phase between f1 and fд is presented in the form of pulses vФЧД, the duration of which is proportional to the phase error. CP has current output and converts signals of the phase error into a sequence of current pulses iЗП of various directivity, which are proportional to the phase error vФЧД. LFF is the loop filter and an integrator of current pulses iЗП from the circuit of the charge pump. VCO is a tunable generator. The frequency of the signal fг on its output depends on the signal level vФНЧ on the control input. DVDR generates a frequency fд by dividing the frequency fг by integer factor N, which is set on external terminals MOD[5 : 0] of the synthesizer. The frequency fд is then sent as feedback to one of inputs of PFD to determine the phase imbalance of signals f1 and fд. DVDR in conjunction with the VCO generates the frequency fд so that during the operation of the PLL it became equal to the reference frequency f1. The step change in the output frequency fвых is equal to the value of frequency f1. Change of division ratio N at a constant reference frequency f0 leads to a change of frequencies fг, fд and fвых. An important parameter of the frequency synthesizer is the settling time of frequency fвых when changing the factor N. In modern devices, the settling time of the output signal of FS is from 20 to 50 µs [5, 6]. Small tuning step between neighboring values of the frequency fвых requires low value of reference frequency f1 on the input of FS. However, this leads to the necessity of increasing the ratio of N and proportional to the maximum spectral density of the phase noise. However, this leads to the necessity of increasing the ratio of N and proportional increase of spectral density of the phase noise. To reduce the spectral density of phase noise, the DPCD is divided into two counters (A and B) with a tunable splitting ratios. This solution allowed us to implement in the FS for the adjustment of the bandwidth a feedback loop, in which the settling time of the output signal (fвых) does not exceed 50 µs. The basis of IP core for SF is the linearized mathematical model (Fig.2) of the frequency synthesizer of (n+1)-th order on the basis of the PLL with LFF of n-th order. For this mathematical model the transfer function T(s) of closed circuit of FS  has the form: form01eng.ai where G(s) is the transfer function of the straight chain, H(s) is the transfer function of the inverse chain, θг(s) is the output phase, θ0(s) is the input reference phase, KФЧД is the transfer coefficient of the discriminator, ZПФ(s) is the impedance of the loop filter, KГУН is the slope of the tuning characteristics of the VCO, s is the complex variable, N is the division ratio of the frequency of DVDR. The definition and analysis of a linearized mathematical model, the substitution of the appropriate parameters of individual blocks allowed to reach in the feedback system the value of phase margin of about 50 degrees, relative short time of transients in the FS and determination of the frequency fвых. In the PFD (Fig.3) the signal f1 with input phase θ0 is added to the feedback signal fд with phase θДПКД, and the phase difference is multiplied by the ratio KГУН. The PFD circuit is based on the dynamic single-phase synchronous triggers that allows to enhance the performance of the detector and to reduce the settling time of the control voltage of VCO. At operation of the CP the logic levels on the inputs UP and DN control the integration of current iЗП on LFF. The pump has original design, includes two current sources with alignment of currents on the basis of an error amplifier in the operational amplifier and precharge blocks to reduce the negative effects when switching current sources. If the current sources of the pump are disabled, the output (OUT) is in a high impedance state, which enables storage of the achieved level of the voltage of control signal vФНЧ. CP has an extended range of the output operating voltage through the use of a low-voltage current mirror and has a lower current leakage, which reduces the spurious components in the spectrum of fвых. The LFF (loop filter) is implemented in the form of the integrating chain of the 3-th order . It determines the dynamic characteristics of the FS and adds additional poles and zeros to the phase-frequency characteristic. The LFF reduces the discrete side components that are formed by CP and VCO in the spectrum of the output signal. The impedance of the filter of the third order is manifested in binomial form: form02eng.ai By changing the variable of impedance in the transfer function of the closed circuit of FS with PLL it is possible to determine the natural frequency of the jitter of the PLL, that is oscillations arising in case of R2 = 0 and R3 = 0. Frequency of the jitter decreases with the increase of the values of capacitors of LFF and decrease in operating current of CP. The VCO is implemented using differential delay elements (Fig.4), which have better noise performance at frequencies up to 1 GHz compared to in-phase elements. Special attention during development was paid to such parameters of the VCO, as the linearity of the transfer characteristic, frequency tuning range and power consumption (Fig.5). IP core of the frequency synthesizer has a register MOD[5 : 0] for adjustment of the factor N = A*B and output PLL_MOD for switch-off a loop of PLL FS. The synthesizer can operate in three modes: when N ≥ 1 and PLL_MOD = 1, the output frequency (Fig.6) FВЫХ = FВХ ∙ A / M, where FВХ is the input frequency, M is the division ratio of the FDRP, A is the division ratio of the counter in DVDR; when N = 0 and PLL_MOD = 1, the PLL loop is enabled and the output frequency FВЫХ = FВХ; when PLL_MOD = 0, the PLL loop is disabled, and the frequency of the output signal FВЫХ = FВХ. General view of the topology of the designed IP core of FS is shown in Fig.7. IP core of the frequency synthesizer is implemented on the base of 5521 gate array family for 0.18 µm process  and has the characteristics presented in table. ■ This paper was created with the financial support of the Ministry of Education and Science of the Russian Federation. Unique identifier RFMEFI58015X0005.