Developing and Investigating 0.35-micron SPICE-model of SOI MOS-transistor With F-type Gate Geometry Using TCAD Instrument-process Modelling System
Similar behaviour is demonstrated by the so-called SoI MOS-transistors with F-type gate, whose topology is presented on Fig. 1.
As compared to MOS-transistors, having H- and T-configuration of the gate , this layout implementation provides a number of advantages, in particular, less area occupied on chip, as well as convenience of routing at the stage of VLSI chip layout design. But it turned out that volt-current characteristics of standard SPICE-model of such MOS-transistor significantly differs from these measurements, which is especially important in modelling characteristics of MOS-transistor with F-type gate in case of small channel width W.
To investigate the differences between measurements data and characteristics of standard SPICE-model of MOS-transistor of the given configuration and to explain them in terms of semiconductor physics, a modelling of its operational parameters inside the system of instrument-process modelling Sentaurus TCAD was carried out.
Fig. 4 depicts the layout of MOS-transistor obtained by means of instrument-process modelling. It should be noted that in the given case polysilicon gate was doped by impurities of both conductivity types, and a portion of transistor channel located under doped by p-type impurity gate also takes part in the process of conductivity-type inversion and channel appearance. We generated an instrument-process model for estimating the effect produced by polysilicon doping with different impurity types, in which polysilicon was doped only by n-type impurity. And then we obtained drain-gate characteristics of both artificially generated and original models. Fig. 5 shows the results of numerical differentiation of obtained drain-gate characteristics, from which it id obvious that due to additional gate doping by opposite conductivity type impurity the form of current dependence on voltage changes. This change is most significant when voltage at the gate is higher than the sum of threshold voltage and a certain constant numerically equal to the width of band gap of silicon.
Besides, series resistance of drain/source regions in MOS-transistor with small gate width is less than that in transistor with large gate width because of additional conducting regions in contacts with transistor’s well.
For developing SPICE-model that could adequately specify the given type of transistor, it was proposed to add two additional transistors in parallel with the main transistor. The first additional MOS-transistor has threshold voltage equal to that of the main transistor and is used for taking into account scaling effect. And the second additional transistor has higher threshold voltage — by value numerically corresponding to band gap width value . The difference in threshold voltage was obtained by means of optimization with further extraction of parameters for new SPICE-model. The width and length of additional transistors gates, as well as values of their series resistances were obtained in the course of optimization by minimizing sum of discrepancy squares between calculated and measured characteristics for transistors with different width and identical length of channel L (L = 0.35 micron).
Consequently, SPICE-model of MOS-transistor with F-type gate was obtained, whose drain-gate characteristics are presented on Figs 6–9.
Summarizing the above said, the authors consider that the scientific value of the research is the obtained subsystem of SPICE-model for SoI MOS-transistor with F-type gate, which adequately describes the features of its electrical characteristics behaviour at small values of the gate width W.
Instrument-process modelling was done using TCAD Sentaurus system installed on the computing server of N. E. Bauman Moscoq State Technical University.
This work was partially supported by the Russian Foundation for Basic Research (Grant 15-07-03116).
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