rus
Special Issue/2019
D. V. Matveev, A. M. Galimov, I. A. Fateev, D. V. Kulikov
Integrated solution for parrying thyristor eff ect for VLSI SoC
Integrated solution for parrying thyristor eff ect for VLSI SoC
The paper considers hardware SEL parry techniques. Test circuits have been developed to obtain characteristics of parasitic latch and to study methods of detecting thyristor effect.
The paper considers hardware SEL parry techniques. Test circuits have been developed to obtain characteristics of parasitic latch and to study methods of detecting thyristor effect.
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