Expressions were obtain for estimating the complexity and speed of decomposition of a multi-bit LUT at a lower-order LUT. A comparison of the complexity and delay in the number of transistors was perform for the decomposition of a multi-bit LUT in the computer mathematics Mathcad system. The features of constructing multi-bit LUTs were determined and various variants of decomposition were evaluate with further increase in the LUT dimension with the subsequent choice of the optimal variant of the adaptive logic module.


Разработка: студия Green Art