The paper presents a technique that allows finding the optimal position of the phase auxiliary clock signal of the receiver. Based on this technique, the controller has been implemented and integrated into the receiver. The simulation results have shown an increase in the opening of eye diagram by 1.8 % of the unit interval horizontally and 38мВ vertically for 10Gb/s data stream passed through the channel with attenuation −23dB at a frequency 5GHz. The receiver is designed in CMOS 65nm technology and operates from the power source 1V.


Разработка: студия Green Art