rus
Issue #9/2018
Tyurin Sergey F., Goncharovskiy Oleg V., Prokhorov Andrey S.
A Fault Tolerant Vote Circuit
A Fault Tolerant Vote Circuit
Reliability means and radiation resistance of digital equipment. For aerospace computer systems is extremely urgent to develop radiation-resistant components. One way to ensure the radiation resistance is the creation of a special architecture — RHBD (Radiation Hardened by Design). This approach includes triple redundancy (Triple Modular Redundancy — TMR) to reduce radiation-induced switching of logic elements (Single Event Transients — SET) and memory elements (Single Event Upset — SEU). FPGA due to the large number of elements configuration memory is not vulnerable to the effects of radiation. Therefore, one-time programmable devices are used, for example, the companies Actel, but flip-flops tripled too. Nevertheless, in the SRAM configurable FPGA Virtex (Xilinx) used triple redundancy with Majority Vote Circuit based on a tristate buffer instead LUT. Such Voter has implementation features that are explored in the article. One of the variants of majority voter for the pins of the FPGA using a minority voting function. Only in this case, no conflict of signals at the outputs of buffers. Describes CMOS implementation of the voters. The paper proposes a fault tolerant CMOS implementation of the Majority Voter and Minority Voter in order to improve reliability and FPGA radiation resistance.
Теги: 3-state buffer majority vote circuit minority vote circuit triple module redundancy схема большинства голосов схема меньшинства голосов тристабильный буфер тройная избыточность
INTRODUCTION
FPGAs are widely used in computer technology [1–4]. There are fault tolerant FPGAs for aerospace computer systems. Radiation Hardened by Design (RHBD) architecture includes the development of redundant structures, for example Triple Modular Redundancy (TMR) [5–7]. This method is supported by the Virtex architecture of Xilinx FPGAs [8, 9]. As a rule, Majority Vote Circuits based on CMOS, NAND, NOR (for Application-Specific Integrated Circuit — ASIC and Uncommitted Logic Array — ULA) and LUT (Look Up Table — for FPGAs) gates are used. It is common practice to use Majority Vote Circuits based on Look-Up Tables (LUTs), on 3-state buffers (BUFT) and Pullup resistor, Majority Vote Circuits based on 3-state buffers with Minority Vote Circuits without Pullup [8].
MAJORITY VOTE CIRCUIT
Triple module redundancy uses three copies of the same circuit and performs a bit-wise “majority vote” on the output of the triplicate circuit [4]. The function of the majority voter is:
V = AB ∨ BC ∨ AC.(1)
The Truth Table (1) is shown in Fig. 1:
Expression (1) is a self-dual function, so:
Eqn001.eps.
The FPGAs majority voters use Look-Up Tables (LUTs).
Eqn002EN.eps
Fig. 2 shows CMOS representation of the Majority Voter.
Fig. 3 shows LUT representation of the Majority Voter.
However, 4 input LUT representations of the majority voter use only one halt of the transistor tree.
STATE BUFFER MAJORITY VOTE CIRCUIT
Fig. 4 shows VirtexTM majority vote circuit (Xilinx) that is based on internal 3-state buffer and uses the Virtex primitive BUFT library instead of Look-Up Tables (LUTs).
An analysis of the device operation makes it possible to establish situations of signal conflict at the output (see Fig. 5).
The simulation of the 3-State Buffer Majority Voter, executed in the NI Multisim 10 system by National Instruments Electronics Workbench Group, shows the incorrectness of such a scheme (see Fig. 6).
Nevertheless, the documentation indicates the use of the so-called Virtex Horizontal Bus Logic [5] that is solving the problem. Fig. 7а, b shows one possible way of constructing the correct scheme obtained by the authors.
The oscillogram in Fig. 7b confirms the realization of the function (1).
STATE BUFFER MAJORITY VOTE CIRCUIT WITH MINORITY VOTE CIRCUIT
Avoiding the conflict of signals is also possible using the 3-State Buffer Majority Vote Circuit with Minority Vote Circuit [6], as seen in Fig. 8.
What is Minority Vote Circuit? This function has the form represented by expression (4):
Eqn003.eps.(4)
The Truth Table (4) is shown in Fig. 9.
Let us make the notation in Fig. 10.
Fig. 11 describes the functioning of the majority vote circuit with the use of Minority Vote Circuit presented on Fig. 10.
M is output of the appropriate voting device for the minority. We can conclude that the channel, which differs from the other two, is turned off by forming the corresponding z-state buffer at the output (see Fig. 11). At the output V, the conjunction O1, O2, O3 is realized.
CMOS IMPLEMENTATION OF THE MINORITY VOTE CIRCUIT
Let us visualize the CMOS implementation of the minority vote function. Fig. 12 shows the simplified CMOS implementation of Minority Voter (as in expression (4) and Fig. 10).
Figs. 13 and 14 show the simulation of the CMOS implementation (Fig. 12) of the Minority Voter.
The simulation confirms the efficiency of the proposed Minority Voter.
VOTERS WITH REDUNDANCY
Fig. 15 shows the known CMOS implementation of the 3-State Buffer.
In order to improve reliability of the 3-State Buffer Majority Vote Circuit we will offer voters with redundancy. Fig. 16 shows the proposed 3-State Buffer with redundancy.
Fig. 17 presents the comparison of the 3-State Buffer with redundancy and without it [10].
Winning is achieved in a considerable range of probabilities as opposed to triple scheme that gets worse when unreserved already at the probability of the order of 0.88. Fig. 18 shows the proposed Minority Voter with redundancy taking into account Mead-Conway limitations [11].
Fig. 19 presents the comparison of the Minority Voter with redundancy and without it.
CONCLUSIONS
A circuit based on a two-stage 3-State Buffer is correct and corresponds to Virtex datasheet. The paper proposes a fault tolerant CMOS implementation of majority and minority voting functions as separate elements in order to improve the performance of redundant circuits without using FPGA logic resources. The simulation of CMOS Minority Vote Circuit within National Instruments Electronics Workbench Group system simulation confirms the efficiency of the proposed element, and the evaluation of the failure-free operation probability shows its high efficiency. Advanced Voters improve radiation hardening of the aerospace computer systems.
REFERENCES
1. Kharchenko V. (editor): Green IT-Engineering. In 2 volumes. Vol. 1. Principles, Components and Models — 593 p.; Vol. 2. Systems, Industry, Society. — 628 p. Ukraine: National Aerospace University KhAI (2014) (In Russian).
2. Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices. Available at: https://www.altera.com.cn/content/dam/alterawww/global/zh_CN/pdfs/literature/hb/stx3/stx3_siii51002.pdf (accessed 26.03.2017).
3. Drozd A., Drozd J., Shapa J., Maevsky D. The Levels of Target Resources Development in Computer Systems. In: Design & Test Symposium (EWDTS), 2014 East-West, pp. 1–5, IEEE, (2014).
4. Mehta, Nikil. An Ultra-Low-Energy, Variation-Tolerant FPGA Architecture Using Component-Specific Mapping. Dissertation (Ph.D), California Institute of Technology. (2013).http://resolver.caltech.edu/CaltechTHESIS:10072012-230900231.
5. Jennifer Susan Hane. A Fault-Tolerant Computer Architecture for Space Vehicle Applications. Available at: http://scholarworks.montana.edu/xmlui/bitstream/handle/1/1423/hanej0512.pdf?sequence=1 (accessed 20.03.2017).
6. Bradley Matush. An Innovative Radiation Hardened by Design Flip-Flop. A Thesis Presented in Partial Fulfillment of the Requirements for the Degree Master of Science. Available at: https://repository.asu.edu/attachments/56273/content/Matush_asu_0010N_10226.pdf (accessed 22.01.2017).
7. Shubham C. Anjankar, Dr. Mahesh T. Kolte. Fault Tolerant and Correction System Using Triple Modular Redundancy. International Journal of Emerging Engineering Research and Technology Vol. 2, Issue 2, May 2014, PP. 187–191. Available at: http://www.ijeert.org/pdf/v2-i2/31.pdf (accessed 26.01.2017).
8. Carl Carmichael. Triple Module Redundancy Design Techniques for Virtex FPGAs Available at: https://www.xilinx.com/support/documentation/application_notes/xapp197.pdf (accessed 22.03.2017).
9. QPro Virtex-II 1.5V Platform FPGAs. DS122 (v3.0) Available at: http://www.xilinx.com/support/documentation/data_sheets/ds122.pdf (accessed 26.03.2017).
10. Kamenskih A. N., Tyurin S. F. The Development of Basic Logic Element for Strictly Self-Timed FPGA. International Conference on Information and Digital Technologies, IDT 2015PP. 128–131 DOI:10.1109/DT.2015.7222962
11. Conway, Lynn. Drafts of the Mead-Conway Textbook, Introduction to VLSI Systems. University of Michigan. Retrieved 9 June 2015.
FPGAs are widely used in computer technology [1–4]. There are fault tolerant FPGAs for aerospace computer systems. Radiation Hardened by Design (RHBD) architecture includes the development of redundant structures, for example Triple Modular Redundancy (TMR) [5–7]. This method is supported by the Virtex architecture of Xilinx FPGAs [8, 9]. As a rule, Majority Vote Circuits based on CMOS, NAND, NOR (for Application-Specific Integrated Circuit — ASIC and Uncommitted Logic Array — ULA) and LUT (Look Up Table — for FPGAs) gates are used. It is common practice to use Majority Vote Circuits based on Look-Up Tables (LUTs), on 3-state buffers (BUFT) and Pullup resistor, Majority Vote Circuits based on 3-state buffers with Minority Vote Circuits without Pullup [8].
MAJORITY VOTE CIRCUIT
Triple module redundancy uses three copies of the same circuit and performs a bit-wise “majority vote” on the output of the triplicate circuit [4]. The function of the majority voter is:
V = AB ∨ BC ∨ AC.(1)
The Truth Table (1) is shown in Fig. 1:
Expression (1) is a self-dual function, so:
Eqn001.eps.
The FPGAs majority voters use Look-Up Tables (LUTs).
Eqn002EN.eps
Fig. 2 shows CMOS representation of the Majority Voter.
Fig. 3 shows LUT representation of the Majority Voter.
However, 4 input LUT representations of the majority voter use only one halt of the transistor tree.
STATE BUFFER MAJORITY VOTE CIRCUIT
Fig. 4 shows VirtexTM majority vote circuit (Xilinx) that is based on internal 3-state buffer and uses the Virtex primitive BUFT library instead of Look-Up Tables (LUTs).
An analysis of the device operation makes it possible to establish situations of signal conflict at the output (see Fig. 5).
The simulation of the 3-State Buffer Majority Voter, executed in the NI Multisim 10 system by National Instruments Electronics Workbench Group, shows the incorrectness of such a scheme (see Fig. 6).
Nevertheless, the documentation indicates the use of the so-called Virtex Horizontal Bus Logic [5] that is solving the problem. Fig. 7а, b shows one possible way of constructing the correct scheme obtained by the authors.
The oscillogram in Fig. 7b confirms the realization of the function (1).
STATE BUFFER MAJORITY VOTE CIRCUIT WITH MINORITY VOTE CIRCUIT
Avoiding the conflict of signals is also possible using the 3-State Buffer Majority Vote Circuit with Minority Vote Circuit [6], as seen in Fig. 8.
What is Minority Vote Circuit? This function has the form represented by expression (4):
Eqn003.eps.(4)
The Truth Table (4) is shown in Fig. 9.
Let us make the notation in Fig. 10.
Fig. 11 describes the functioning of the majority vote circuit with the use of Minority Vote Circuit presented on Fig. 10.
M is output of the appropriate voting device for the minority. We can conclude that the channel, which differs from the other two, is turned off by forming the corresponding z-state buffer at the output (see Fig. 11). At the output V, the conjunction O1, O2, O3 is realized.
CMOS IMPLEMENTATION OF THE MINORITY VOTE CIRCUIT
Let us visualize the CMOS implementation of the minority vote function. Fig. 12 shows the simplified CMOS implementation of Minority Voter (as in expression (4) and Fig. 10).
Figs. 13 and 14 show the simulation of the CMOS implementation (Fig. 12) of the Minority Voter.
The simulation confirms the efficiency of the proposed Minority Voter.
VOTERS WITH REDUNDANCY
Fig. 15 shows the known CMOS implementation of the 3-State Buffer.
In order to improve reliability of the 3-State Buffer Majority Vote Circuit we will offer voters with redundancy. Fig. 16 shows the proposed 3-State Buffer with redundancy.
Fig. 17 presents the comparison of the 3-State Buffer with redundancy and without it [10].
Winning is achieved in a considerable range of probabilities as opposed to triple scheme that gets worse when unreserved already at the probability of the order of 0.88. Fig. 18 shows the proposed Minority Voter with redundancy taking into account Mead-Conway limitations [11].
Fig. 19 presents the comparison of the Minority Voter with redundancy and without it.
CONCLUSIONS
A circuit based on a two-stage 3-State Buffer is correct and corresponds to Virtex datasheet. The paper proposes a fault tolerant CMOS implementation of majority and minority voting functions as separate elements in order to improve the performance of redundant circuits without using FPGA logic resources. The simulation of CMOS Minority Vote Circuit within National Instruments Electronics Workbench Group system simulation confirms the efficiency of the proposed element, and the evaluation of the failure-free operation probability shows its high efficiency. Advanced Voters improve radiation hardening of the aerospace computer systems.
REFERENCES
1. Kharchenko V. (editor): Green IT-Engineering. In 2 volumes. Vol. 1. Principles, Components and Models — 593 p.; Vol. 2. Systems, Industry, Society. — 628 p. Ukraine: National Aerospace University KhAI (2014) (In Russian).
2. Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices. Available at: https://www.altera.com.cn/content/dam/alterawww/global/zh_CN/pdfs/literature/hb/stx3/stx3_siii51002.pdf (accessed 26.03.2017).
3. Drozd A., Drozd J., Shapa J., Maevsky D. The Levels of Target Resources Development in Computer Systems. In: Design & Test Symposium (EWDTS), 2014 East-West, pp. 1–5, IEEE, (2014).
4. Mehta, Nikil. An Ultra-Low-Energy, Variation-Tolerant FPGA Architecture Using Component-Specific Mapping. Dissertation (Ph.D), California Institute of Technology. (2013).http://resolver.caltech.edu/CaltechTHESIS:10072012-230900231.
5. Jennifer Susan Hane. A Fault-Tolerant Computer Architecture for Space Vehicle Applications. Available at: http://scholarworks.montana.edu/xmlui/bitstream/handle/1/1423/hanej0512.pdf?sequence=1 (accessed 20.03.2017).
6. Bradley Matush. An Innovative Radiation Hardened by Design Flip-Flop. A Thesis Presented in Partial Fulfillment of the Requirements for the Degree Master of Science. Available at: https://repository.asu.edu/attachments/56273/content/Matush_asu_0010N_10226.pdf (accessed 22.01.2017).
7. Shubham C. Anjankar, Dr. Mahesh T. Kolte. Fault Tolerant and Correction System Using Triple Modular Redundancy. International Journal of Emerging Engineering Research and Technology Vol. 2, Issue 2, May 2014, PP. 187–191. Available at: http://www.ijeert.org/pdf/v2-i2/31.pdf (accessed 26.01.2017).
8. Carl Carmichael. Triple Module Redundancy Design Techniques for Virtex FPGAs Available at: https://www.xilinx.com/support/documentation/application_notes/xapp197.pdf (accessed 22.03.2017).
9. QPro Virtex-II 1.5V Platform FPGAs. DS122 (v3.0) Available at: http://www.xilinx.com/support/documentation/data_sheets/ds122.pdf (accessed 26.03.2017).
10. Kamenskih A. N., Tyurin S. F. The Development of Basic Logic Element for Strictly Self-Timed FPGA. International Conference on Information and Digital Technologies, IDT 2015PP. 128–131 DOI:10.1109/DT.2015.7222962
11. Conway, Lynn. Drafts of the Mead-Conway Textbook, Introduction to VLSI Systems. University of Michigan. Retrieved 9 June 2015.
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