Optimizing Capacitor Array Layout in SAR ADC
Analog-to-digital converters (ADCs) are widely used both as standalone general purpose integrated circuits (ICs), and as part of application specific ICs, and as part of such ICs as system on a chip (SoC), which can contain up to 100 and more signal conversion channels . There is a tendency to use ADC in self-diagnostic systems of SoC, including built-in means of monitoring power, temperature, and parameters of a number of blocks [2–4]. One of the reasons is that many SoCs have a complex, adaptively configurable cluster power supply system, as well as a dynamically reconfigurable architecture . This requires monitoring the current values of the block’s operating parameters, temperature, and in some cases, monitoring the integrity of the signals in several buses, for example, in power rails [6, 7]. SoCs for mission-critical applications developed in compliance with the functional safety rules and standards should also have built-in self-diagnosis and testing means .
In systems of multi-point hardware monitoring, SoCs use either a built-in ADC with an analog multiplexer or an array of several ADCs placed in the locations of controlled blocks. In many cases such a distributed topology is preferable. For monitoring temperatures, voltages, and currents in SoCs with the distributed data acquisition system, most efficient ADC types are those of successive approximation register (SAR), of medium accuracy, moderate speed, with low power consumption, surpassing after ADC types , on condition that the occupied area is minimized. Such ADCs supplemented by an array of high-speed sample-hold devices at the points of control are also used to monitor dynamic parameters, for example, the integrity of signals on a chip . Along with the use as IP-blocks of SoCs, these ADCs are used as standalone ICs.
Most SAR ADCs implemented in CMOS technology use a digital-to-analog converter (DAC) based on charge balancing in an array of capacitors with binary weighted capacitances to generate reference voltages during the balancing process. When designing such ADCs that are meant for the considered applications, it is necessary to optimize the layout of their main unit — the array of capacitors to minimize the occupied area while simultaneously ensuring the required level of accuracy. That is the subject of this paper. It deals with the design features of the layout of the capacitor array related to the optimization of its geometry, in particular, the choice of its dimensions, capacitance of its unit capacitor and the distance between the capacitors and signal lines.
ANALYSIS OF THE EFFECT OF CAPACITOR ARRAY DIMENSIONS
It has been shown that the non-binary component of parasitic capacitance is the main source of the error of differential nonlinearity . The non-binary component of the stray capacitance of a compound capacitor that consists of unit capacitors is due to the capacitance between the top plates of unit capacitors included in this compound capacitor and the signal lines connected to the bottom plates of other capacitors. Therefore, the stray capacitance Сs of each capacitor can be estimated as follows: Сs = Сp∙ k, where Сp is the stray capacitance of a unit capacitor on the signal line passing next to it; k is the number of unit capacitors that are adjacent to the signal line connected to the capacitor under consideration, but which are not part of this capacitor. Fig. 1 shows a stray capacitance from the top plate of a unit capacitor to the signal line.
The dependence of the stray capacitance Сp(a, h) between a unit square-shaped capacitor and the adjacent signal line on the capacitor size and the distance to the signal line can be approximated by the following expression:
where a is the length or width of the capacitor; h is the distance from the capacitor to the signal line; h0 is an adjustable parameter whose value is approximately equal to the sum of the thickness of the dielectric between the metal layers and the distance between the edges of the top and bottom plates of capacitor; CE is a specific edge capacitance between two layers of metallization (F/m). Its value is given in a process design kit (PDK);
Estimation of the relative error of the differential nonlinearity for each of the N codes is given by:
The numerator of this expression is the maximum value of the difference between the stray capacitance Ci of the largest capacitor switching on from code i – 1 to code i and the sum of the stray capacitances of the other switching capacitors. C0 is a capacitance of the unit capacitor.
Then the dependence of differential nonlinearity on the size of the elements of capacitor array can be given by:
where CU is a specific capacitance of a unit capacitor (F/m2). Its value is given in PDK.
Fig. 2 shows the relationship between the differential nonlinearity and the size and location of the capacitors. It also shows two planes of constraints, one of which corresponds to the maximum permissible differential nonlinearity error (horizontal plane), and the other determines the maximum permissible size of the capacitor and the distance between the capacitor and the nearest signal line (vertical plane).
The restriction associated with the dimensions is the plane that is given by the expression L = a + h, where L is the parameter that determines the maximum size of the base cell of the array and hence characterizes the size of the entire array because it is a multiple of L.
The section of the error surface by this plane can be given by the following relation:
This formula shows the dependence of the maximum error of the differential nonlinearity on the characteristic size of the capacitor for given constraints on the size of the capacitor array.
The function DNLmax(a) has a minimum at:
The optimal value of h is given by:
Thus, aopt и hopt are optimal dimensions of the array cell with given restriction on its maximum size. Substitution of these values into the formula for differential nonlinearity gives the relationship between the maximum error and the size of the capacitor array:
The resulting relation allows us to estimate the nonlinearity error for a given size of the capacitor array, as well as the minimum array size necessary to achieve a given level of accuracy.
The results of the analysis were the basis of the methodology for capacitor array layout optimization in the 10-bit SAR ADC implemented in 0.18μm CMOS.
SUCCESSIVE APPROXIMATION ADC
Fig. 3 shows a schematic diagram of ADC. It is implemented using a conventional single-ended charge balancing architecture. To reduce the occupied area, the capacitor array of the DAC is divided into two sub-arrays. One of them is controlled by seven most significant bits of the code from the output of the SAR, the other is controlled by three least significant bits. The sub-arrays are connected to each other via capacitor Ca, acting as an attenuator. The capacitance of the unit capacitor is 90fF.
Fig. 4 shows the ADC layout. The height of the block is 230µm, which does not exceed the width of three typical pads. Therefore, it can be used to build multichannel chips with ADC in each channel.
The ADC was developed using radiation hardening by design techniques. In particular, edgeless n-channel MOSFETs with additional guard rings were used, as well as automatic offset compensation in stages of the comparator as shown in Fig. 5.
The ADC has been manufactured in XFAB XPO18 commercial 0.18μm CMOS process. A feature of this technology is the availability of 5V MOS transistors, which provides a wide range of supply voltages.
Fig. 6 shows the static performance measurements results of the ADC test samples. The level of differential nonlinearity (DNL) does not exceed half the less significant bit (LSB). Integral nonlinearity (INL) is less than 1.5 LSB. The summary of the ADC measured performance is given in Table 1.
The paper presents an analysis of the effect of the layout dimensions of elements of a capacitor array on the differential nonlinearity of SAR ADC, as well as gives estimation of the accuracy of the array depending on its size. The obtained results allow estimating the ADC layout dimension and choosing the optimal values of capacitors at the early stages of design.
As an example of practical application of the research results, we have presented a block of a micro-power SAR ADC that has a 10-bit resolution and a speed of 400ksps with a current consumption less than 0.1mA. The level of differential nonlinearity does not exceed 0.5LSB without using background calibration.
The ADC is designed as part of application-specific IC for spacecraft on-board applications, and also as a standalone IC of multichannel ADC.
The authors consider that the results of the analysis of the effect of the layout parameters of the capacitor array on the accuracy of the SAR ADC are novel.
1. Zou X., Liu L., Cheong J. H., Yao L., Li P., Cheng M.-Y., Goh W. H., Rajkumar R., Dawe G. S., Cheng K.-W., Je M. A 100-Channel 1-mW Implantable Neural Recording IC // IEEE Transactions on Circuits and Systems I: Regular Papers. 2013. Vol. 60. No. 10, P. 2584–2596.
2. Zjajo A., van der Meijs N., van Leuken R. Adaptive Thermal Monitoring of Deep-Submicron CMOS VLSI Circuits // Journal of Low Power Electronics. 2013. Vol. 9. No. 4, P. 1–11.
3. Sonmez U., Sebastiano F., Makinwa K. A. A. Compact Thermal-Diffusivity-Based Temperature Sensors in 40-nm CMOS for SoC Thermal Monitoring // IEEE Journal of Solid-State Circuits, 2017. Vol. 52. No. 3, P. 834–843.
4. Noguchi K., Nagata M. An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration // IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2007. Vol. 15. No. 10, P. 1101–1110.
5. Sivakumar R., Jothi D. Recent Trends in Low Power VLSI Design // International Journal of Computer and Electrical Engineering. 2014. Vol. 6. No. 6, P. 509–523.
6. Lee P. H., Lee H. Y., Lee H. B., Jang Y. C. An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces with Source-Synchronous Clock // IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2017. Vol. 25. No. 4, P. 1386–1396.
7. Whatmough P. N., Das S., Hadjilambrou Z., Bull D. M. Power Integrity Analysis of a 28nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor // IEEE Journal of Solid-State Circuits. 2017. Vol. 52. No. 6, P. 1643–1654.
8. Katoh K., Doumar A., Ito H. Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift / Proceedings of 11th IEEE International On-Line Testing Symposium. 2005. P. 203–204.
9. Zhou H., Gui X., Gao P. Design of a 12-bit 0.83 MS/s SAR ADC for an IPMI SoC / Proceedings of 28th IEEE International System-on-Chip Conference (SOCC). Beijing. 2015. P. 175–179.
10. Osipov D. L., Bocharov Yu. I., Butuzov V. A. The Behavioral Model of a Split Capacitor Array Involved in the Successive Approximation Register ADC and Taking into Account the Effect of Parasitic Capacitors // Russian Microelectronics. 2013. Vol. 42. No 4, P. 253–259.