rus
Issue #1/2023
K.A.Tsarik, O.B.Chukanova, E.A.Kozlovskaya
DESIGN FEATURES OF HETEROSTRUCTURES FOR CONSTRUCTION OF GaN NORMALLY-OFF TRANSISTORS FOR POWER MONOLITHIC INTEGRATED CIRCUITS
DESIGN FEATURES OF HETEROSTRUCTURES FOR CONSTRUCTION OF GaN NORMALLY-OFF TRANSISTORS FOR POWER MONOLITHIC INTEGRATED CIRCUITS
DOI: https://doi.org/10.22184/1993-8578.2023.16.1.70.79
This paper considers the key dependencies of characteristics of the normally-off transistors on GaN heterostructures parameters. Thicknesses and concentrations of dopants in the layers of the heterostructure are determined. As a result of the simulation, the current-voltage characteristics of a p-channel field-effect transistor and an n-channel transistor with a p-type gate layer were obtained.
This paper considers the key dependencies of characteristics of the normally-off transistors on GaN heterostructures parameters. Thicknesses and concentrations of dopants in the layers of the heterostructure are determined. As a result of the simulation, the current-voltage characteristics of a p-channel field-effect transistor and an n-channel transistor with a p-type gate layer were obtained.
Теги: heterostructures monolithic integrated circuits normally-off transistors гетероструктуры монолитные интегральные схемы нормально-закрытые транзисторы
INTRODUCTION
Gallium nitride (GaN) and related semiconductor alloys (such as AlGaN, InGaN, etc.) have repeatedly been mentioned as promising materials for the next generation of high-power and high-frequency electronic devices. As standard, GaN/AlGaN transistors are normally-on. Power applications require normally-off devices to ensure safe operation and a simple gate control configuration. Creating a monolithic circuit based on such devices will enable complementary pairing and logic circuits, and will expand the electronic component base in Russia.
In order to design normally-off transistors it is necessary to ensure that there are no charge carriers in the transistor channel below the gate at zero voltages across such transistors. For this purpose, a heterostructure must be designed to allow precise control of the threshold voltage and to change it towards positive values. Threshold voltage depends on Schottky barrier height, conduction band gap in AlGaN/GaN heterojunction, dAlGaN barrier thickness, Al share in AlGaN, concentration of donor impurity in AlGaN, dielectric permittivity of barrier layer, and polarization charge density [1].
Over the years, several solutions have been proposed to achieve normally-off operation: implanting fluorine ions under the gate [2], deepening the gate and using a metal-insulator-semiconductor (MIS) structure [3], cascode connection of the normally-on and MOSFET [4] and using the p-GaN layer under the gate [2].
When fluorine ions are implanted, negative charge of the ions contributes to depletion of the channel and leads to a positive threshold voltage Vth. In recent work [5] it has been shown that F-ions can exhibit instability at high electrical voltages, leading to changes in threshold voltage, increased leakage currents and reduced mobility. In order to partly reduce this disadvantage, plasma etching in inductively coupled plasma (ICP) is carried out using very low power.
The use of a gate-type MIS structure buried in an AlGaN barrier ensures that gate leakage is effectively minimised and the threshold voltage is above one volt. The main drawbacks of this approach are instability of the threshold voltage due to traps in dielectrics and the time-dependent dielectric breakdown of the thin insulator layer [6]. Therefore, in such transistors it is important to select the correct type of material for sub-gate dielectric.
In cascode connection of a normally-on high voltage GaN transistor and a low voltage silicon MOS transistor, the latter controls the on/off state of the pair, while the GaN HEMT (which has high field stability) holds voltage in the off-state. The advantages of this solution are the very good threshold voltage stability, ability to use standard Si drivers, and the use of a normally-on HEMT whose fabrication process and reliability are well known. On the other hand, complexity of the cascode connection presents the major disadvantage.
The p-GaN type layer lifts the band diagram of the heterostructure resulting in complete depletion of two-dimensional electron gas (2DEG) at zero gate bias. Specific problems of p-GaN-gate transistors are the time-dependent degradation and trapping effects related to acceptor impurity in the form of NiO, a promising insulating material for GaN devices due to its wide bandgap (4 eV) and relatively high dielectric constant of 11.9 (i.e., almost three times higher than that of the commonly used SiO2), can be selected as a semiconductor under the gate. An important aspect related to NiO is the possibility to tune its electronic properties by changing the growth conditions of the material. In fact, under certain conditions, NiO p-type semiconducting layers can be obtained and used to form normally closed GaN HEMT, but it is quite difficult to control some of the process steps, which can affect 2DEG properties [7].
On the basis of heterostructures with p-GaN layer the so-called platforms are formed which include different types of devices: normally-on GaN transistors, normally-off n-channel and normally-off p-channel devices [8]. These platforms allow of reducing and simplifying circuit assembly, as well as design complementary pairs based on GaN structures.
Thus, in this paper physical modelling is used to study behaviour of the band structure by varying the barrier layer and spacer layer parameters. The behaviour of characteristics of a GaN-based normal-closed transistor at different values of the barrier layer thickness has been studied. A possibility of normally-off p-channel formation or normally-on GaN transistors with variation of p-GaN layer parameters is also studied.
RESEARCH METHODS
The study was carried out using simulation in Sentaurus TCAD (Technology Computer Aided Design) software package. This software is developed for semiconductor modelling and allows of simulating both the fabrication and behaviour of semiconductor devices. TCAD uses Newton’s method for solving Poisson’s equations, continuity equations, etc. These equations provide necessary information to determine specific physical parameters of the device. Sentaurus TCAD also takes the GaN piezoelectric polarisation physics into account. Another advantage of Sentaurus TCAD is that its library of provided semiconductor devices includes a HEMT structure which can be used as a reference when modelling transistors.
The presence of piezoelectric polarisation leads to an interface charge. The value of the interface charge density σ is determined by polarisation difference of the contacting substances. For AlGaN/GaN heterostructures, the magnitude of the charge σ can be calculated using the elastic constants GaN, AlN and Vegard›s rule for the solid solution AlxGa1-xN. The sign of the charge σ depends on the interface type: Ga-face when the GaN layer ends with a gallium atom, and N-face with a nitrogen atom.
For TCAD calculations, one can use the interface charge accounting technique with the simplest classical diffusion-drift model, or one can use the built-in polarisation packages that take into account both spontaneous and piezoelectric polarisation. The presence of polarisation charge on the GaN surface between the electrodes complicates the operation of devices, so various passivation layers are used, which can also be modelled in Sentaurus TCAD.
In GaN/AlGaN structures it is possible to obtain layer concentration values up to 6 · 1013 cm-2. In fact, this is not the case. As the Al mole fraction in the barrier layer increases, the lattice mismatch increases, leading to stress relaxation and formation of dislocations in the barrier layer and reducing mobility m. In reality, the structures with Al mole fraction x <0.3 and Ns concentration about 1 · 1013 cm-2 are grown.
Thus, the barrier layer parameters have a significant influence on device type, threshold voltage and output characteristics. It is therefore important to consider in detail the effect of the parameters of this layer specifically on our structure.
For modelling purposes a structure was used which contained the following layers: p-GaN 50 nm thick, AlGaN with Al 20% mole fraction of 9 nm, GaN channel layer, AlGaN buffer with Al 5% mole fraction, AlN nucleation layer, and substrate (Fig.1). The device design was chosen as follows: gate length 1 μm, drain-gate distance 6 μm and source-gate distance 1 μm.
To calculate the concentration in the channel a quantum mechanical problem has to be solved but, as shown in [9], the same result is obtained if we limit ourselves to using the simplest classical diffusion-drift model. At zero offsets at the gate, a band diagram of the structure (Fig.2) and distribution of charge carrier density depending on the barrier layer thickness, mole fraction of aluminium in it were constructed, and influence of p-GaN layer parameters on transistor characteristics and the influence of AlN layer thickness were studied.
RESULTS AND DISCUSSION
By varying the barrier layer thickness and mole fraction of aluminium in it and by measuring the carrier concentration in the channel, an evaluation curve of the device type was constructed (Fig.3). If the structure has the barrier layer parameters in region I, the device is normally-on, while if it has parameters in region II, it is normally-off. It is necessary to take values of parameters closer to y-axis, i.e. with thickness less than 20 nm and mole fraction of Al more than 20 % to make a device with decent drain currents, though for power applications it is not the most important parameter of a transistor. In our case, a barrier layer thickness of 15 nm and an Al content of 23% were chosen.
It is also important to consider how exactly the barrier layer parameters affect the main characteristics of the transistor – the threshold voltage and drain current in the open state. The threshold voltage of a normally-off device must be positive, and, following the publications of foreign scientists – more than 1 V [10]. Fig.4 and Fig.5 show the dependences of transistor drain current at 3.5 V at the gate and threshold voltage on the barrier layer thickness and dependence of transistor drain current at 3.5V at the gate and threshold voltage on mole fraction of Al in it. Thus, the optimal barrier parameters to form a normally-off p-GaN gate transistor are 15 nm thickness and 23% mole fraction of Al in the barrier layer. Then the drain current at 3.5 V at the gate will be about 350 mA/mm and threshold voltage is about 1.5 V.
The other important parameter is the AlN layer thickness. In order to deplete the channel at zero bias with electrodes, the barrier layer thickness must be small enough, as already shown. The presence of an AlN spacer layer increases the effective barrier thickness inversely, so its thickness should be chosen as small as possible. The critical thickness of the spacer layer has been estimated using the methodology described above. The thickness of this layer should not be more than 1.5 nm (Fig.6). When the thickness of AlN increases higher than 1.5 nm, concentration of electrons in the GaN layer will start to increase sharply.
The influence of the p-GaN layer on the device characteristics was also investigated. Based on the dependence of charge carriers concentration in the channel on p-layer, its critical thickness of 40 nm was found. At greater layer thickness the device is normally-off and layer thickness has no effect on their characteristics. Similarly, the critical degree of doping – 4 · 1017 cm-3 has been revealed from dependence of charge carriers concentration in the channel on p-layer impurity concentration. To obtain the normally-off state, the doping of the p-layer must be greater than this value. In practice, however, this parameter is poorly controlled. As a rule, concentration of the introduced impurity is known and what percentage of it is activated during growth is unknown.
A normally-off p-channel field effect transistor can also be formed on a single wafer in a single process cycle on the described heterostructure. It will enable to form GaN-based complementary pairs, create different types of devices in a single process cycle, which will simplify circuit assembly. To form a p-channel transistor, n+-GaN must be built up under the gate to ensure normally-off device behaviour (Fig.7).
For a normally-off p-channel transistor a device type evaluation method was also developed (Fig.8). The main parameters are channel layer parameters – Mg impurity concentration and p-layer thickness in this case. Similarly, if the structure has p-layer parameters in the I region, the transistor is normal-open. To create a universal platform when selecting parameters for p-channel transistor it is necessary to take into account parameters of n-channel transistor so that it too is normally-off (region III in Fig.8).
Thus, the following composition of heterostructure for the investigated platform was chosen: p-GaN with thickness 80 nm, AlGaN with mole fraction Al 23% 15 nm, GaN channel layers, AlGaN buffer with mole fraction Al 5%, AlN nucleation layer, and substrate. Figure 9 shows the calculated volt-current characteristics for these devices. A normally-off p-channel field effect transistor with gate length, drain-gate and source-gate of 1 µm each has a drain current at -3 V on the gate of the order of -0.9 mA/mm. By varying topology of the device, varying the length and width, it will be possible to achieve similar levels of current to create a complementary pair.
As mentioned above, an n-channel device is normally closed due to the p-GaN layer, which ‘lifts’ the conduction band, thereby depleting the transistor channel. Let us consider physics of a normally-off p-channel field effect transistor. In this case the entire p-layer itself is already channelized and its parameters directly impact the device current. In order to close it, it is necessary, to "overlap" the entire p-layer with the help of the RCD, or use some other approach.
In the literature, similarly to the standard approaches, it is proposed to deepen the gate into the p-layer and treat the sub-gate region with oxygen [11]. In this paper we propose to grow n+-GaN in the gate region to form a p-GaN/n-GaN heterojunction, which OPD will control the channel. Here, another problem may arise. Such a p-channel transistor turns out to be two-channel. One hole channel is the entire p-GaN layer, and the electronic channel is due to polarisation on the AlGaN/GaN heterojunction, which is overlapped at rest due to the p-layer above. The electronic channel does not impact the operation of the device as it works at positive bias, so the electronic channel is always overlapped.
CONCLUSIONS
Modelling of GaN-based normally-off transistors is demonstrated. The influence of heterostructure parameters on behaviour of a normally-off n-channel transistor with a p-GaN gate and a normally-off p-channel transistor controlled by a p-n junction has been investigated. The optimal heterostructure design for different types of devices in a single process cycle has been selected. The techniques for determining device types by key parameters of heterostructures were developed. The physics of device operation was considred discussed.
Thus, a normally-off n-channel transistor with 1 µm long p-gate, 1 µm long source-gate and 6 µm drain-gate has a maximum drain current of 350 mA/mm at 3.5 V at the gate. A normally-off p-channel junction-driven p-n junction transistor with 1 µm electrode spacing has a drain current at -3 V at the gate of about -0.9 mA/mm.
The developed devices will make it possible to create so-called "platforms" with different types of devices that open up a possibility of forming complementary pairs and different circuits in a single cycle, thereby expanding electronic component base (ECB) of Russia. Moreover, the developed devices will be able to replace the power GaAs devices and increase their power (in 5G technologies, for example).
ACKNOWLEDGEMENTS
The study was completed with the financial support of the Ministry of Education and Science, project FSMR-2022-0004.
PEER REVIEW INFO
Editorial board thanks the anonymous reviewer(s) for their contribution to the peer review of this work. It is also grateful for their consent to publish papers on the journal’s website and SEL eLibrary eLIBRARY.RU.
Declaration of Competing Interest. The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
Gallium nitride (GaN) and related semiconductor alloys (such as AlGaN, InGaN, etc.) have repeatedly been mentioned as promising materials for the next generation of high-power and high-frequency electronic devices. As standard, GaN/AlGaN transistors are normally-on. Power applications require normally-off devices to ensure safe operation and a simple gate control configuration. Creating a monolithic circuit based on such devices will enable complementary pairing and logic circuits, and will expand the electronic component base in Russia.
In order to design normally-off transistors it is necessary to ensure that there are no charge carriers in the transistor channel below the gate at zero voltages across such transistors. For this purpose, a heterostructure must be designed to allow precise control of the threshold voltage and to change it towards positive values. Threshold voltage depends on Schottky barrier height, conduction band gap in AlGaN/GaN heterojunction, dAlGaN barrier thickness, Al share in AlGaN, concentration of donor impurity in AlGaN, dielectric permittivity of barrier layer, and polarization charge density [1].
Over the years, several solutions have been proposed to achieve normally-off operation: implanting fluorine ions under the gate [2], deepening the gate and using a metal-insulator-semiconductor (MIS) structure [3], cascode connection of the normally-on and MOSFET [4] and using the p-GaN layer under the gate [2].
When fluorine ions are implanted, negative charge of the ions contributes to depletion of the channel and leads to a positive threshold voltage Vth. In recent work [5] it has been shown that F-ions can exhibit instability at high electrical voltages, leading to changes in threshold voltage, increased leakage currents and reduced mobility. In order to partly reduce this disadvantage, plasma etching in inductively coupled plasma (ICP) is carried out using very low power.
The use of a gate-type MIS structure buried in an AlGaN barrier ensures that gate leakage is effectively minimised and the threshold voltage is above one volt. The main drawbacks of this approach are instability of the threshold voltage due to traps in dielectrics and the time-dependent dielectric breakdown of the thin insulator layer [6]. Therefore, in such transistors it is important to select the correct type of material for sub-gate dielectric.
In cascode connection of a normally-on high voltage GaN transistor and a low voltage silicon MOS transistor, the latter controls the on/off state of the pair, while the GaN HEMT (which has high field stability) holds voltage in the off-state. The advantages of this solution are the very good threshold voltage stability, ability to use standard Si drivers, and the use of a normally-on HEMT whose fabrication process and reliability are well known. On the other hand, complexity of the cascode connection presents the major disadvantage.
The p-GaN type layer lifts the band diagram of the heterostructure resulting in complete depletion of two-dimensional electron gas (2DEG) at zero gate bias. Specific problems of p-GaN-gate transistors are the time-dependent degradation and trapping effects related to acceptor impurity in the form of NiO, a promising insulating material for GaN devices due to its wide bandgap (4 eV) and relatively high dielectric constant of 11.9 (i.e., almost three times higher than that of the commonly used SiO2), can be selected as a semiconductor under the gate. An important aspect related to NiO is the possibility to tune its electronic properties by changing the growth conditions of the material. In fact, under certain conditions, NiO p-type semiconducting layers can be obtained and used to form normally closed GaN HEMT, but it is quite difficult to control some of the process steps, which can affect 2DEG properties [7].
On the basis of heterostructures with p-GaN layer the so-called platforms are formed which include different types of devices: normally-on GaN transistors, normally-off n-channel and normally-off p-channel devices [8]. These platforms allow of reducing and simplifying circuit assembly, as well as design complementary pairs based on GaN structures.
Thus, in this paper physical modelling is used to study behaviour of the band structure by varying the barrier layer and spacer layer parameters. The behaviour of characteristics of a GaN-based normal-closed transistor at different values of the barrier layer thickness has been studied. A possibility of normally-off p-channel formation or normally-on GaN transistors with variation of p-GaN layer parameters is also studied.
RESEARCH METHODS
The study was carried out using simulation in Sentaurus TCAD (Technology Computer Aided Design) software package. This software is developed for semiconductor modelling and allows of simulating both the fabrication and behaviour of semiconductor devices. TCAD uses Newton’s method for solving Poisson’s equations, continuity equations, etc. These equations provide necessary information to determine specific physical parameters of the device. Sentaurus TCAD also takes the GaN piezoelectric polarisation physics into account. Another advantage of Sentaurus TCAD is that its library of provided semiconductor devices includes a HEMT structure which can be used as a reference when modelling transistors.
The presence of piezoelectric polarisation leads to an interface charge. The value of the interface charge density σ is determined by polarisation difference of the contacting substances. For AlGaN/GaN heterostructures, the magnitude of the charge σ can be calculated using the elastic constants GaN, AlN and Vegard›s rule for the solid solution AlxGa1-xN. The sign of the charge σ depends on the interface type: Ga-face when the GaN layer ends with a gallium atom, and N-face with a nitrogen atom.
For TCAD calculations, one can use the interface charge accounting technique with the simplest classical diffusion-drift model, or one can use the built-in polarisation packages that take into account both spontaneous and piezoelectric polarisation. The presence of polarisation charge on the GaN surface between the electrodes complicates the operation of devices, so various passivation layers are used, which can also be modelled in Sentaurus TCAD.
In GaN/AlGaN structures it is possible to obtain layer concentration values up to 6 · 1013 cm-2. In fact, this is not the case. As the Al mole fraction in the barrier layer increases, the lattice mismatch increases, leading to stress relaxation and formation of dislocations in the barrier layer and reducing mobility m. In reality, the structures with Al mole fraction x <0.3 and Ns concentration about 1 · 1013 cm-2 are grown.
Thus, the barrier layer parameters have a significant influence on device type, threshold voltage and output characteristics. It is therefore important to consider in detail the effect of the parameters of this layer specifically on our structure.
For modelling purposes a structure was used which contained the following layers: p-GaN 50 nm thick, AlGaN with Al 20% mole fraction of 9 nm, GaN channel layer, AlGaN buffer with Al 5% mole fraction, AlN nucleation layer, and substrate (Fig.1). The device design was chosen as follows: gate length 1 μm, drain-gate distance 6 μm and source-gate distance 1 μm.
To calculate the concentration in the channel a quantum mechanical problem has to be solved but, as shown in [9], the same result is obtained if we limit ourselves to using the simplest classical diffusion-drift model. At zero offsets at the gate, a band diagram of the structure (Fig.2) and distribution of charge carrier density depending on the barrier layer thickness, mole fraction of aluminium in it were constructed, and influence of p-GaN layer parameters on transistor characteristics and the influence of AlN layer thickness were studied.
RESULTS AND DISCUSSION
By varying the barrier layer thickness and mole fraction of aluminium in it and by measuring the carrier concentration in the channel, an evaluation curve of the device type was constructed (Fig.3). If the structure has the barrier layer parameters in region I, the device is normally-on, while if it has parameters in region II, it is normally-off. It is necessary to take values of parameters closer to y-axis, i.e. with thickness less than 20 nm and mole fraction of Al more than 20 % to make a device with decent drain currents, though for power applications it is not the most important parameter of a transistor. In our case, a barrier layer thickness of 15 nm and an Al content of 23% were chosen.
It is also important to consider how exactly the barrier layer parameters affect the main characteristics of the transistor – the threshold voltage and drain current in the open state. The threshold voltage of a normally-off device must be positive, and, following the publications of foreign scientists – more than 1 V [10]. Fig.4 and Fig.5 show the dependences of transistor drain current at 3.5 V at the gate and threshold voltage on the barrier layer thickness and dependence of transistor drain current at 3.5V at the gate and threshold voltage on mole fraction of Al in it. Thus, the optimal barrier parameters to form a normally-off p-GaN gate transistor are 15 nm thickness and 23% mole fraction of Al in the barrier layer. Then the drain current at 3.5 V at the gate will be about 350 mA/mm and threshold voltage is about 1.5 V.
The other important parameter is the AlN layer thickness. In order to deplete the channel at zero bias with electrodes, the barrier layer thickness must be small enough, as already shown. The presence of an AlN spacer layer increases the effective barrier thickness inversely, so its thickness should be chosen as small as possible. The critical thickness of the spacer layer has been estimated using the methodology described above. The thickness of this layer should not be more than 1.5 nm (Fig.6). When the thickness of AlN increases higher than 1.5 nm, concentration of electrons in the GaN layer will start to increase sharply.
The influence of the p-GaN layer on the device characteristics was also investigated. Based on the dependence of charge carriers concentration in the channel on p-layer, its critical thickness of 40 nm was found. At greater layer thickness the device is normally-off and layer thickness has no effect on their characteristics. Similarly, the critical degree of doping – 4 · 1017 cm-3 has been revealed from dependence of charge carriers concentration in the channel on p-layer impurity concentration. To obtain the normally-off state, the doping of the p-layer must be greater than this value. In practice, however, this parameter is poorly controlled. As a rule, concentration of the introduced impurity is known and what percentage of it is activated during growth is unknown.
A normally-off p-channel field effect transistor can also be formed on a single wafer in a single process cycle on the described heterostructure. It will enable to form GaN-based complementary pairs, create different types of devices in a single process cycle, which will simplify circuit assembly. To form a p-channel transistor, n+-GaN must be built up under the gate to ensure normally-off device behaviour (Fig.7).
For a normally-off p-channel transistor a device type evaluation method was also developed (Fig.8). The main parameters are channel layer parameters – Mg impurity concentration and p-layer thickness in this case. Similarly, if the structure has p-layer parameters in the I region, the transistor is normal-open. To create a universal platform when selecting parameters for p-channel transistor it is necessary to take into account parameters of n-channel transistor so that it too is normally-off (region III in Fig.8).
Thus, the following composition of heterostructure for the investigated platform was chosen: p-GaN with thickness 80 nm, AlGaN with mole fraction Al 23% 15 nm, GaN channel layers, AlGaN buffer with mole fraction Al 5%, AlN nucleation layer, and substrate. Figure 9 shows the calculated volt-current characteristics for these devices. A normally-off p-channel field effect transistor with gate length, drain-gate and source-gate of 1 µm each has a drain current at -3 V on the gate of the order of -0.9 mA/mm. By varying topology of the device, varying the length and width, it will be possible to achieve similar levels of current to create a complementary pair.
As mentioned above, an n-channel device is normally closed due to the p-GaN layer, which ‘lifts’ the conduction band, thereby depleting the transistor channel. Let us consider physics of a normally-off p-channel field effect transistor. In this case the entire p-layer itself is already channelized and its parameters directly impact the device current. In order to close it, it is necessary, to "overlap" the entire p-layer with the help of the RCD, or use some other approach.
In the literature, similarly to the standard approaches, it is proposed to deepen the gate into the p-layer and treat the sub-gate region with oxygen [11]. In this paper we propose to grow n+-GaN in the gate region to form a p-GaN/n-GaN heterojunction, which OPD will control the channel. Here, another problem may arise. Such a p-channel transistor turns out to be two-channel. One hole channel is the entire p-GaN layer, and the electronic channel is due to polarisation on the AlGaN/GaN heterojunction, which is overlapped at rest due to the p-layer above. The electronic channel does not impact the operation of the device as it works at positive bias, so the electronic channel is always overlapped.
CONCLUSIONS
Modelling of GaN-based normally-off transistors is demonstrated. The influence of heterostructure parameters on behaviour of a normally-off n-channel transistor with a p-GaN gate and a normally-off p-channel transistor controlled by a p-n junction has been investigated. The optimal heterostructure design for different types of devices in a single process cycle has been selected. The techniques for determining device types by key parameters of heterostructures were developed. The physics of device operation was considred discussed.
Thus, a normally-off n-channel transistor with 1 µm long p-gate, 1 µm long source-gate and 6 µm drain-gate has a maximum drain current of 350 mA/mm at 3.5 V at the gate. A normally-off p-channel junction-driven p-n junction transistor with 1 µm electrode spacing has a drain current at -3 V at the gate of about -0.9 mA/mm.
The developed devices will make it possible to create so-called "platforms" with different types of devices that open up a possibility of forming complementary pairs and different circuits in a single cycle, thereby expanding electronic component base (ECB) of Russia. Moreover, the developed devices will be able to replace the power GaAs devices and increase their power (in 5G technologies, for example).
ACKNOWLEDGEMENTS
The study was completed with the financial support of the Ministry of Education and Science, project FSMR-2022-0004.
PEER REVIEW INFO
Editorial board thanks the anonymous reviewer(s) for their contribution to the peer review of this work. It is also grateful for their consent to publish papers on the journal’s website and SEL eLibrary eLIBRARY.RU.
Declaration of Competing Interest. The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
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