rus
Special Issue/2019
Yu. M. Gerasimov, N. G. Grigoryev, A. V. Kobylyatskiy, Ya. Ya. Petrichkovich, T. V. Solokhina
From The First CMOS Transistors To The Radiation-Hardened Nanometer CMOS Systems-on-chip
From The First CMOS Transistors To The Radiation-Hardened Nanometer CMOS Systems-on-chip
The paper highlights the main questions of radiation-hardened CMOS IC design — from the first CMOS transistors in 1968 to modern nanometer “systems-on-chip” (SoC). The modern radiation-hardened CMOS IC are designed on bulk CMOS technologies ranging from 250 nm to 90 nm. The features of the VLSI radiation-hardness-by-design have been analyzed. A number of competitive systems-on-chip and SRAM chips have been designed based on radiation-hardened standard cell and IO libraries and IP-blocks.
The paper highlights the main questions of radiation-hardened CMOS IC design — from the first CMOS transistors in 1968 to modern nanometer “systems-on-chip” (SoC). The modern radiation-hardened CMOS IC are designed on bulk CMOS technologies ranging from 250 nm to 90 nm. The features of the VLSI radiation-hardness-by-design have been analyzed. A number of competitive systems-on-chip and SRAM chips have been designed based on radiation-hardened standard cell and IO libraries and IP-blocks.
Readers feedback
