rus
Issue #1/2026
A.Y.Chistiakov, M.A.Zapletina
EXPERIENCE OF APPLICATION OF CATBOOST OPEN-SOURCE GRADIENT BOOSTING LIBRARY FOR ROUTING STAGE WITHIN FPGA PHYSICAL SYNTHESIS
EXPERIENCE OF APPLICATION OF CATBOOST OPEN-SOURCE GRADIENT BOOSTING LIBRARY FOR ROUTING STAGE WITHIN FPGA PHYSICAL SYNTHESIS
https://doi.org/10.22184/1993-8578.2026.19.1.80.88.
A model for predicting routing time has been developed, forming the core of a software module for tuning input parameters to accelerate the routing stage using the X-CAD computer-aided design tool for implementing digital circuits on FPGAs. Computational experiments demonstrated a reduction of routing solution generation time by an average of 1.5 times for the 5510TS028 FPGA.
A model for predicting routing time has been developed, forming the core of a software module for tuning input parameters to accelerate the routing stage using the X-CAD computer-aided design tool for implementing digital circuits on FPGAs. Computational experiments demonstrated a reduction of routing solution generation time by an average of 1.5 times for the 5510TS028 FPGA.
Теги: digital circuits fpga routing x-cad computer-aided design плис сапр х-cad трассировка цифровые схемы
Received: 27.01.2026 | Accepted: 30.01.2026 | DOI: https://doi.org/10.22184/1993-8578.2026.19.1.80.88
Original paper
Experience of application of CatBoost open-source gradient boosting library for routing stage within FPGA physical synthesis
A.Y.Chistiakov1, Engineer Researcher, ORCID: 0000-0002-5972-8317 / chis.alexandr2018@yandex.ru
M.A.Zapletina1, Cand. of Sci. (Tech), Senior Researcher, ORCID: 0000-0001-9845-7823
Abstract. A model for predicting routing time has been developed, forming the core of a software module for tuning input parameters to accelerate the routing stage using the X-CAD computer-aided design tool for implementing digital circuits on FPGAs. Computational experiments demonstrated a reduction of routing solution generation time by an average of 1.5 times for the 5510TS028 FPGA.
Keywords: routing, X-CAD computer-aided design, FPGA, digital circuits
For citation: T.O. Sovetnikov, V.M. Ganshin, I.V. Yaminsky. Experience of application of catboost open-source gradient boosting library for routing stage within FPGA physical synthesis. NANOINDUSTRY. 2026. Vol. 19. No. 1. PP. 80–88. https://doi.org/10.22184/1993-8578.2026.19.1.80.88.
INTRODUCTION
In the current conditions of large-scale import substitution, there is a need for increasingly widespread use of domestic programmable logic integrated circuits (FPGAs). A key factor influencing the design results quality based on them is computer-aided design (CAD) systems, their performance and ease of use.
The route for designing circuits in the FPGA database consists of the stages of logical synthesis, physical synthesis (including clustering, placement and routing), digital modelling, static timing analysis, and firmware creation. The most time-consuming and computationally intensive stage is the preliminary routing stage, which is part of the physical synthesis stage. In addition, it is this stage that is significantly affected by the trend towards greater integration of new microcircuits. In this regard, accelerating this stage plays an important role in terms of CAD efficiency.
One possible way to speed up the tracing stage is to use machine learning (ML) methods. Currently, leading developers of CAD for FPGAs (Altera, AMD) have already had their first successful experience of implementing intelligent techniques in their products, and research in this area appears to be the most promising.
This paper describes experience of using the CatBoost open machine learning library [1] to select tracing algorithm parameters in the X-CAD CAD system for FPGAs [2]. Section 2 reviews existing approaches to of machine learning application methods in the FPGA circuit design flow. Section 3 is devoted to the tools used in this work. Section 4 describes the idea of applying the CatBoost model to the tracing stage and its implementation as part of the design route in the X-CAD CAD system. Section 5 presents the results of computational experiments and an analysis of the impact of the developed approach on the final characteristics of the designed circuits. Sections 6 and 7 describe some of the difficulties encountered during development and the conclusion, respectively.
ANALYSIS OF EXISTING METHODS FOR APPLYING MACHINE LEARNING IN THE DESIGN PROCESS OF CIRCUITS IN THE FPGA DATABASE
Machine learning technologies, which have undergone rapid development in recent years, are used in a variety of fields. CAD for FPGAs is no exception, with machine learning methods being incorporated into design algorithms to significantly improve the quality of the resulting solutions. For example, AMD, the second largest developer in terms of sales on the global FPGA market, uses these technologies in its Vivado CAD [3]. Their use allows for more efficient logical optimisation, circuit delay estimation, and certain other operations. Collectively, the application of machine learning methods has made it possible to significantly speed up route traversal while simultaneously improving the quality of design results.
Developers are actively working to apply machine learning methods to improve individual design stages, particularly routing. Routing is the final stage of physical synthesis in the FPGA circuit design process. As a result, the design circuits obtained at the logic synthesis stage are mapped onto the available FPGA routing resources. This connects the logic elements and other FPGAs components (input/output cells, complex functional blocks) to each other. The timing characteristics of the resulting circuits depend directly on the quality of the routing, so improving the routing algorithms used in CAD remains an important area of research. Current work in this area is presented below.
One of the tasks addressed in [4] is predicting the separability of design circuits based on data from previous design stages. The DLRoute prediction model is based on a convolutional neural network. It takes four congestion maps as input data, reflecting the length of interconnections per unit area, the number of design circuit terminals, and the number of split circuits (having external terminals) within two different areas of the crystal surface. Based on the analysis of the maps, the model predicts the layout routability with this placement. Using this approach made it possible to skip certain design stages for layouts with good routability, thereby speeding up the routing process by 48.3%. The total length of interconnections increased by 4.3%.
The paper [5] describes development of a generative-competitive neural network, which was used to create a heat map of the potential location of overloaded areas of the crystal at the tracing stage, based on data on the placement and interconnection of FPGA elements. Based on the results of its analysis, changes can be made to the placement of the designed circuit to reduce the complexity of the routing task, which will ultimately lead to improved routability and higher quality of the resulting routing solution.
Another category of scientific work includes research on machine learning methods application at the top level in relation to software for designing integrated circuits, for example, for selecting CAD input parameters that improve the quality of design results. An example of such work is [6]. It describes the machine learning methods application for tuning the parameters of the algorithm for placing circuits that include complex functional blocks. On a number of test circuits, the proposed solution demonstrated the fundamental possibility of achieving improvements in both classic industry metrics of area, delay, and power consumption, as well as in the number of design rule violations (DRC) and total interconnect length.
SOFTWARE USED
1. CatBoost Library
The basis for development a predictive model in this work was the open machine learning library CatBoost in the Python programming language, developed by Yandex. The models formed on its basis are based on the gradient boosting method. This involves combining several weak machine learning algorithms into one strong one, where each subsequent algorithm takes into account the errors of the previous one. CatBoost is optimised to work with categorical features, which allows them to be used without pre-processing. The library is used in many Yandex services for weather forecasting, search queries, and other tasks.
The key factors that influenced the choice of CatBoost as a tool for gaining experience in applying ML methods in X-CAD CAD were as follows: the library is a domestic development; models created with its help require less training time and make predictions faster than their counterparts; it is accompanied by high-quality, detailed documentation and numerous publicly available examples of use.
2. Optuna framework
To develop a model with the highest prediction accuracy, the CatBoost library requires the configuration of model hyperparameters, such as the selection of the number of training iterations. Manual iterative selection of these parameters is possible, but this approach is not optimal because the relationship between hyperparameters and training results is not obvious. The Optuna framework [7] comes to the rescue in solving this problem by automating the selection of hyperparameters. This tool supports a set of optimisation and selection interruption algorithms, allowing the framework to be configured in the most effective way for a specific task. Optuna is also implemented in Python, which lowers the threshold for specialists to apply it with the CatBoost library.
IDEA OF APPLICATION AND IMPLEMENTATION
1. The place of the model in the design process
Routing is one of the stages of the standard route for designing circuits on FPGAs, which is shown in Fig.1. In the X-CAD CAD system, it is performed using a modification of the PathFinder routing algorithm [8], which has a number of configuration parameters that control the direction and dynamics of the search for a routing solution. Preliminary experiments have shown that by selecting these parameters, it is possible to significantly reduce the routing time and improve the quality of the result.
By default, the parameter set values and tracing algorithm dynamics remain unchanged, regardless of the characteristics of the designed circuit and its placement on the FPGA chip. The idea behind using the CatBoost library is to create a predictive model for determining the characteristics of the tracing stage results based on circuit placement data, and then use the data obtained to select individual parameter set values for each circuit being designed. The proposed approach is designed to eliminate the labour-intensive manual selection of tuning parameters and speed up the final solution.
To implement the idea, an auxiliary software module was developed as part of the X-CAD CAD system, shown schematically in Fig.1 on the right and highlighted with a dotted line. The main structures included in it are a regression model based on the CatBoost library and a parameter selection tool that acts as a link between the model and the tracing module in the CAD software core.
From the previous stages of the route, the parameter selection tool receives information about the placement of the circuit (in matrix form) and the percentage of the FPGA crystal area filled. The tool then generates dozens of variations of the set of tuning parameters based on predefined ranges of values and step sizes. Once the parameter sets have been formed, the CatBoost model launch cycle begins. The number of iterations in the cycle is equal to the number of sets. During each iteration, one of the generated sets, the matrix layout of the circuit, and the crystal fill percentage are passed to the model, which uses this data to predict the trace time and returns it to the matching tool. At the end of the cycle, the obtained trace time predictions are compared with each other, and the set of parameters that yielded the shortest time is passed back to the route to control the tracing algorithm.
2. Preparation of the data set
Training the CatBoost regression model requires a large dataset containing trace parameter values, placement, crystal fill percentage, and corresponding trace time. To develop such a dataset, circuits were selected from the open test sets LGSynth’89, IWLS’2005, ISCAS’85, ISCAS’89, and projects from opencores.org. The target crystal selected is the 5510TS028 FPGA, which has 17,920 programmable logic elements (PLEs). For the circuits, the initial part of the design route was completed in X-CAD to generate their placement. The percentage of crystal area coverage varied from 0.1 to 35%. Based on the options obtained, the circuit tracing stage was launched with random variations in the tracing parameters. Thus, a training data set was formed, consisting of 2,000 records, each containing 5 parameters of the tracing algorithm [2]:
The record also includes the crystal fill percentage, placement information in the form of binary value matrices (0 – free PLL, 1 – used in circuit placement), and the trace time obtained in seconds as target data.
3. Training models
The predictive model was trained on a prepared dataset using the CatBoostRegressor strategy. The dataset was automatically split into training and test sets using CatBoost tools, with a 90% to 10% ratio, respectively. Model hyperparameter tuning was carried out using the Optuna framework, utilizing the TPESampler optimization algorithm and the SuccessiveHalvingPruner early stopping algorithm during the process.
The selected hyperparameter values are as follows:
4. Development of auxiliary software tools
The routing parameter selection software is designed to automate the interaction of the X-CAD design route with a CatBoost-based predictive model and is a program written in Tcl. For each of the parameters required by the model to predict routing time, a range of values and a step for generating variations are specified. Due to the extremely large amount of time required to exhaustively go through all combinations of tracing parameters, the most suitable values for each parameter are calculated separately. Thus, five cycles are performed, in each of which one of the parameters is selected. Parameters that have not yet been selected are replaced with the values used by default at the tracing stage in X-CAD. Information about the FPGA utilization and placement is the same for all runs of the CatBoost model. The value of the tunable parameter for which the model predicted the shortest trace time is considered the most suitable. Once all parameters have been selected, they are passed to the tracing algorithm.
Due to the regression-based type of the predictive model, in the case of small schemes, there is a possibility of obtaining a negative predicted time. If this occurs, the negative value is replaced with the minimum positive value is 1 second.
RESULTS OF COMPUTATIONAL EXPERIMENTS
Computational experiments conducted by running the X-CAD design flow for a set of 86 typical circuits on the target FPGA 5510TC028 showed a reduction in routing time by an average of 1.5 times for circuits with a utilization rate of more than 5% (Fig.2). For circuits with a utilization rate of less than 5%, some acceleration in routing was also observed; however, the routing time for them is comparable to the time required for the parameter selection stage, making the use of the developed tools impractical.
The critical path delay in the current model was not an optimization criterion in this study, which is why the value of this metric increased on average by 10.5% for circuits with an occupancy rate of more than 5%. The number of tracing resources used decreased on average by 1.5% for similar circuits.
DISCUSSION
One of the main drawbacks of the approach considered is the need to carry out a time-consuming process of retraining the model after each significant update of the X-CAD tracing algorithm. In addition, forming a high-quality training dataset in the form of a large sample of test circuits that ensures sufficient variability of characteristics presents a certain challenge.
An important aspect characteristic of forming a training dataset for ML methods for FPGA design is taking into account the features of the target programmable integrated circuit architectures, including their quantitative characteristics. For instance, the 5510TC028 chip used for computational experiments in the current work contains 192 input-output cells, which significantly limits the possible selection of circuits for implementation based on it. As a result, one can observe a certain heterogeneity in training and test data sets in terms of the fill percentage. The number of schemes that provide a high fill percentage is significantly lower than the number of small schemes in the set, which is presumably the reason for the low accuracy in predicting trace time.
In addition, the methods of representing placement data, which would allow the model to use them as efficiently as possible, require refinement and in-depth study. The method using binary value matrices does not account for the relationships between logical cells, and in the case of designing small circuits, placement in this form represents a highly sparse matrix.
CONCLUSIONS
The paper presents an approach to selecting parameters for a tracing algorithm using a predictive model based on the open-source machine learning library CatBoost. A dataset was created based on the results of X-CAD CAD runs, and a regression model was trained. The model’s hyperparameters were tuned using the Optuna framework. Based on the results of computational experiments, the proposed approach demonstrated a reduction in routing time by an average of 1.5 times for designs with a target FPGA 5510TC028 utilization of over 5%. The critical path delay increased by an average of 10.5%, while the number of routing resources used decreased by an average of 1.5% for similar designs.
PEER REVIEW INFO
Editorial board thanks the anonymous reviewer(s) for their contribution to the peer review of this work. It is also grateful for their consent to publish papers on the journal’s website and SEL eLibrary eLIBRARY.RU.
Declaration of Competing Interest. The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
Original paper
Experience of application of CatBoost open-source gradient boosting library for routing stage within FPGA physical synthesis
A.Y.Chistiakov1, Engineer Researcher, ORCID: 0000-0002-5972-8317 / chis.alexandr2018@yandex.ru
M.A.Zapletina1, Cand. of Sci. (Tech), Senior Researcher, ORCID: 0000-0001-9845-7823
Abstract. A model for predicting routing time has been developed, forming the core of a software module for tuning input parameters to accelerate the routing stage using the X-CAD computer-aided design tool for implementing digital circuits on FPGAs. Computational experiments demonstrated a reduction of routing solution generation time by an average of 1.5 times for the 5510TS028 FPGA.
Keywords: routing, X-CAD computer-aided design, FPGA, digital circuits
For citation: T.O. Sovetnikov, V.M. Ganshin, I.V. Yaminsky. Experience of application of catboost open-source gradient boosting library for routing stage within FPGA physical synthesis. NANOINDUSTRY. 2026. Vol. 19. No. 1. PP. 80–88. https://doi.org/10.22184/1993-8578.2026.19.1.80.88.
INTRODUCTION
In the current conditions of large-scale import substitution, there is a need for increasingly widespread use of domestic programmable logic integrated circuits (FPGAs). A key factor influencing the design results quality based on them is computer-aided design (CAD) systems, their performance and ease of use.
The route for designing circuits in the FPGA database consists of the stages of logical synthesis, physical synthesis (including clustering, placement and routing), digital modelling, static timing analysis, and firmware creation. The most time-consuming and computationally intensive stage is the preliminary routing stage, which is part of the physical synthesis stage. In addition, it is this stage that is significantly affected by the trend towards greater integration of new microcircuits. In this regard, accelerating this stage plays an important role in terms of CAD efficiency.
One possible way to speed up the tracing stage is to use machine learning (ML) methods. Currently, leading developers of CAD for FPGAs (Altera, AMD) have already had their first successful experience of implementing intelligent techniques in their products, and research in this area appears to be the most promising.
This paper describes experience of using the CatBoost open machine learning library [1] to select tracing algorithm parameters in the X-CAD CAD system for FPGAs [2]. Section 2 reviews existing approaches to of machine learning application methods in the FPGA circuit design flow. Section 3 is devoted to the tools used in this work. Section 4 describes the idea of applying the CatBoost model to the tracing stage and its implementation as part of the design route in the X-CAD CAD system. Section 5 presents the results of computational experiments and an analysis of the impact of the developed approach on the final characteristics of the designed circuits. Sections 6 and 7 describe some of the difficulties encountered during development and the conclusion, respectively.
ANALYSIS OF EXISTING METHODS FOR APPLYING MACHINE LEARNING IN THE DESIGN PROCESS OF CIRCUITS IN THE FPGA DATABASE
Machine learning technologies, which have undergone rapid development in recent years, are used in a variety of fields. CAD for FPGAs is no exception, with machine learning methods being incorporated into design algorithms to significantly improve the quality of the resulting solutions. For example, AMD, the second largest developer in terms of sales on the global FPGA market, uses these technologies in its Vivado CAD [3]. Their use allows for more efficient logical optimisation, circuit delay estimation, and certain other operations. Collectively, the application of machine learning methods has made it possible to significantly speed up route traversal while simultaneously improving the quality of design results.
Developers are actively working to apply machine learning methods to improve individual design stages, particularly routing. Routing is the final stage of physical synthesis in the FPGA circuit design process. As a result, the design circuits obtained at the logic synthesis stage are mapped onto the available FPGA routing resources. This connects the logic elements and other FPGAs components (input/output cells, complex functional blocks) to each other. The timing characteristics of the resulting circuits depend directly on the quality of the routing, so improving the routing algorithms used in CAD remains an important area of research. Current work in this area is presented below.
One of the tasks addressed in [4] is predicting the separability of design circuits based on data from previous design stages. The DLRoute prediction model is based on a convolutional neural network. It takes four congestion maps as input data, reflecting the length of interconnections per unit area, the number of design circuit terminals, and the number of split circuits (having external terminals) within two different areas of the crystal surface. Based on the analysis of the maps, the model predicts the layout routability with this placement. Using this approach made it possible to skip certain design stages for layouts with good routability, thereby speeding up the routing process by 48.3%. The total length of interconnections increased by 4.3%.
The paper [5] describes development of a generative-competitive neural network, which was used to create a heat map of the potential location of overloaded areas of the crystal at the tracing stage, based on data on the placement and interconnection of FPGA elements. Based on the results of its analysis, changes can be made to the placement of the designed circuit to reduce the complexity of the routing task, which will ultimately lead to improved routability and higher quality of the resulting routing solution.
Another category of scientific work includes research on machine learning methods application at the top level in relation to software for designing integrated circuits, for example, for selecting CAD input parameters that improve the quality of design results. An example of such work is [6]. It describes the machine learning methods application for tuning the parameters of the algorithm for placing circuits that include complex functional blocks. On a number of test circuits, the proposed solution demonstrated the fundamental possibility of achieving improvements in both classic industry metrics of area, delay, and power consumption, as well as in the number of design rule violations (DRC) and total interconnect length.
SOFTWARE USED
1. CatBoost Library
The basis for development a predictive model in this work was the open machine learning library CatBoost in the Python programming language, developed by Yandex. The models formed on its basis are based on the gradient boosting method. This involves combining several weak machine learning algorithms into one strong one, where each subsequent algorithm takes into account the errors of the previous one. CatBoost is optimised to work with categorical features, which allows them to be used without pre-processing. The library is used in many Yandex services for weather forecasting, search queries, and other tasks.
The key factors that influenced the choice of CatBoost as a tool for gaining experience in applying ML methods in X-CAD CAD were as follows: the library is a domestic development; models created with its help require less training time and make predictions faster than their counterparts; it is accompanied by high-quality, detailed documentation and numerous publicly available examples of use.
2. Optuna framework
To develop a model with the highest prediction accuracy, the CatBoost library requires the configuration of model hyperparameters, such as the selection of the number of training iterations. Manual iterative selection of these parameters is possible, but this approach is not optimal because the relationship between hyperparameters and training results is not obvious. The Optuna framework [7] comes to the rescue in solving this problem by automating the selection of hyperparameters. This tool supports a set of optimisation and selection interruption algorithms, allowing the framework to be configured in the most effective way for a specific task. Optuna is also implemented in Python, which lowers the threshold for specialists to apply it with the CatBoost library.
IDEA OF APPLICATION AND IMPLEMENTATION
1. The place of the model in the design process
Routing is one of the stages of the standard route for designing circuits on FPGAs, which is shown in Fig.1. In the X-CAD CAD system, it is performed using a modification of the PathFinder routing algorithm [8], which has a number of configuration parameters that control the direction and dynamics of the search for a routing solution. Preliminary experiments have shown that by selecting these parameters, it is possible to significantly reduce the routing time and improve the quality of the result.
By default, the parameter set values and tracing algorithm dynamics remain unchanged, regardless of the characteristics of the designed circuit and its placement on the FPGA chip. The idea behind using the CatBoost library is to create a predictive model for determining the characteristics of the tracing stage results based on circuit placement data, and then use the data obtained to select individual parameter set values for each circuit being designed. The proposed approach is designed to eliminate the labour-intensive manual selection of tuning parameters and speed up the final solution.
To implement the idea, an auxiliary software module was developed as part of the X-CAD CAD system, shown schematically in Fig.1 on the right and highlighted with a dotted line. The main structures included in it are a regression model based on the CatBoost library and a parameter selection tool that acts as a link between the model and the tracing module in the CAD software core.
From the previous stages of the route, the parameter selection tool receives information about the placement of the circuit (in matrix form) and the percentage of the FPGA crystal area filled. The tool then generates dozens of variations of the set of tuning parameters based on predefined ranges of values and step sizes. Once the parameter sets have been formed, the CatBoost model launch cycle begins. The number of iterations in the cycle is equal to the number of sets. During each iteration, one of the generated sets, the matrix layout of the circuit, and the crystal fill percentage are passed to the model, which uses this data to predict the trace time and returns it to the matching tool. At the end of the cycle, the obtained trace time predictions are compared with each other, and the set of parameters that yielded the shortest time is passed back to the route to control the tracing algorithm.
2. Preparation of the data set
Training the CatBoost regression model requires a large dataset containing trace parameter values, placement, crystal fill percentage, and corresponding trace time. To develop such a dataset, circuits were selected from the open test sets LGSynth’89, IWLS’2005, ISCAS’85, ISCAS’89, and projects from opencores.org. The target crystal selected is the 5510TS028 FPGA, which has 17,920 programmable logic elements (PLEs). For the circuits, the initial part of the design route was completed in X-CAD to generate their placement. The percentage of crystal area coverage varied from 0.1 to 35%. Based on the options obtained, the circuit tracing stage was launched with random variations in the tracing parameters. Thus, a training data set was formed, consisting of 2,000 records, each containing 5 parameters of the tracing algorithm [2]:
- factor_bt – directed search influence coefficient;
- maxstep_bt – depth of construction of reverse trees of directed search;
- factor_vp – coefficient of influence of tracing resource overload;
- factor_vh – coefficient of influence of tracing resource overload on previous iterations;
- max_path_w – maximum weight of the tracing path.
The record also includes the crystal fill percentage, placement information in the form of binary value matrices (0 – free PLL, 1 – used in circuit placement), and the trace time obtained in seconds as target data.
3. Training models
The predictive model was trained on a prepared dataset using the CatBoostRegressor strategy. The dataset was automatically split into training and test sets using CatBoost tools, with a 90% to 10% ratio, respectively. Model hyperparameter tuning was carried out using the Optuna framework, utilizing the TPESampler optimization algorithm and the SuccessiveHalvingPruner early stopping algorithm during the process.
The selected hyperparameter values are as follows:
- learning_rate – 0,05;
- iterations – 200;
- depth – 8;
- boosting_type – Plain.
4. Development of auxiliary software tools
The routing parameter selection software is designed to automate the interaction of the X-CAD design route with a CatBoost-based predictive model and is a program written in Tcl. For each of the parameters required by the model to predict routing time, a range of values and a step for generating variations are specified. Due to the extremely large amount of time required to exhaustively go through all combinations of tracing parameters, the most suitable values for each parameter are calculated separately. Thus, five cycles are performed, in each of which one of the parameters is selected. Parameters that have not yet been selected are replaced with the values used by default at the tracing stage in X-CAD. Information about the FPGA utilization and placement is the same for all runs of the CatBoost model. The value of the tunable parameter for which the model predicted the shortest trace time is considered the most suitable. Once all parameters have been selected, they are passed to the tracing algorithm.
Due to the regression-based type of the predictive model, in the case of small schemes, there is a possibility of obtaining a negative predicted time. If this occurs, the negative value is replaced with the minimum positive value is 1 second.
RESULTS OF COMPUTATIONAL EXPERIMENTS
Computational experiments conducted by running the X-CAD design flow for a set of 86 typical circuits on the target FPGA 5510TC028 showed a reduction in routing time by an average of 1.5 times for circuits with a utilization rate of more than 5% (Fig.2). For circuits with a utilization rate of less than 5%, some acceleration in routing was also observed; however, the routing time for them is comparable to the time required for the parameter selection stage, making the use of the developed tools impractical.
The critical path delay in the current model was not an optimization criterion in this study, which is why the value of this metric increased on average by 10.5% for circuits with an occupancy rate of more than 5%. The number of tracing resources used decreased on average by 1.5% for similar circuits.
DISCUSSION
One of the main drawbacks of the approach considered is the need to carry out a time-consuming process of retraining the model after each significant update of the X-CAD tracing algorithm. In addition, forming a high-quality training dataset in the form of a large sample of test circuits that ensures sufficient variability of characteristics presents a certain challenge.
An important aspect characteristic of forming a training dataset for ML methods for FPGA design is taking into account the features of the target programmable integrated circuit architectures, including their quantitative characteristics. For instance, the 5510TC028 chip used for computational experiments in the current work contains 192 input-output cells, which significantly limits the possible selection of circuits for implementation based on it. As a result, one can observe a certain heterogeneity in training and test data sets in terms of the fill percentage. The number of schemes that provide a high fill percentage is significantly lower than the number of small schemes in the set, which is presumably the reason for the low accuracy in predicting trace time.
In addition, the methods of representing placement data, which would allow the model to use them as efficiently as possible, require refinement and in-depth study. The method using binary value matrices does not account for the relationships between logical cells, and in the case of designing small circuits, placement in this form represents a highly sparse matrix.
CONCLUSIONS
The paper presents an approach to selecting parameters for a tracing algorithm using a predictive model based on the open-source machine learning library CatBoost. A dataset was created based on the results of X-CAD CAD runs, and a regression model was trained. The model’s hyperparameters were tuned using the Optuna framework. Based on the results of computational experiments, the proposed approach demonstrated a reduction in routing time by an average of 1.5 times for designs with a target FPGA 5510TC028 utilization of over 5%. The critical path delay increased by an average of 10.5%, while the number of routing resources used decreased by an average of 1.5% for similar designs.
PEER REVIEW INFO
Editorial board thanks the anonymous reviewer(s) for their contribution to the peer review of this work. It is also grateful for their consent to publish papers on the journal’s website and SEL eLibrary eLIBRARY.RU.
Declaration of Competing Interest. The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
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